Abstract: A lithium nickel cobalt manganese composite oxide cathode material includes a plurality of secondary particles. Each secondary particle consists of aggregates of fine primary particles. Each secondary particle includes lithium nickel cobalt manganese composite oxide, which is expressed as LiaNi1-b-cCobMncO2. An average formula of each secondary particle satisfies one condition of 0.9?a?1.2, 0.08?b?0.34, 0.1?c?0.4, and 0.18?b+c?0.67. The lithium nickel cobalt manganese composite oxide has a structure with different chemical compositions of primary particles from the surface toward core of each of the secondary particles. The primary particle with rich Mn content near the surface and the primary particle with rich Ni content in the core of the secondary particle of the lithium nickel cobalt manganese composite oxide cathode material have provided the advantages of high safety and high capacity.

Abstract: Methods of forming a Co cap on a Cu interconnect in or through an ULK ILD with improved selectivity while protecting an ULK ILD surface are provided. Embodiments include providing a Cu filled via in an ULK ILD; depositing a Co precursor and H2 over the Cu-filled via and the ULK ILD, the Co precursor and H2 forming a Co cap over the Cu-filled via; depositing an UV cured methyl over the Co cap and the ULK ILD; performing an NH3 plasma treatment after depositing the UV cured methyl; and repeating the steps of depositing a Co precursor through performing an NH3 plasma treatment to remove impurities from the Co cap.

Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract: Integrated circuits with tungsten components having a smooth surface and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming a nucleation layer overlying a substrate and within a cavity, where the nucleation layer includes tungsten. A nucleation layer thickness is reduced, and a fill layer if formed overlying the nucleation layer.

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.

Abstract: Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate.

Abstract: A light sensing device includes a substrate, a plurality of light sensing elements and a cover. The plurality of light sensing elements are disposed on the substrate for sensing light. The cover is utilized for sheltering the plurality of light sensing elements, wherein the cover includes a hole for passing the light. A set of the plurality of light sensing elements is selected to be enabled according to a location of the hole relative to the plurality of light sensing elements.

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

Abstract: A coupling element, an injection molding object with the coupling element implanted therein are provided. The coupling element has two reversely extended fixing ribs. The injection mold has a first mold and a second mold. The first mold has a first molding cavity and two positioning blocks separated by the first molding cavity. The second mold has a second molding cavity. When the first mold and the second mold are shut together and their molding cavities combine to define a closed room, the positioning blocks hold the coupling element by clamping the fixing ribs so the coupling element is suspended in midair of the closed room.

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

Abstract: An improved method for fabricating a semiconductor device is provided to decrease substrate gouging during oxide spacer formation. The method includes: forming a gate structure on a substrate; depositing an oxide layer along the sidewalls of the gate structure and on the substrate; removing some of the oxide layer to define oxide spacers along sidewalls of the gate structure; and performing an isotropic etch process to remove a residual portion of the oxide layer.

Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Abstract: A mobile communication device with a processor is provided. The processor determines whether an Inter-Radio Access Technology (IRAT) procedure is ongoing when receiving a request for a Mobile Originated (MO) call, starts a first guard timer in response to the IRAT procedure being ongoing, and performs an Access Domain Selection (ADS) for making the MO call in response to the IRAT procedure being completed and the first guard timer not expiring.

Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

Abstract: A fixing mount of a bicycle carrier contains a support rod of a bicycle carrier, a body, at least one cable tie, a connector, and a retainer. The body includes a large-diameter end, a through hole, and a small-diameter end. The large-diameter end has a first arcuate supporting face, a second arcuate supporting face and a third arcuate supporting face. The small-diameter end has a locking groove, and the body also includes plural locking elements. The connector includes a recess, a convex bottom surface, two coupling tabs, and each coupling tab has a concaved top surface and an aperture. The connector further includes plural first extending pieces, and each first extending piece has a first pore. Between any two adjacent extending blocks is defined a notch. The retainer includes at least one second extending piece and a plurality of pegs, and each extending piece has a second pore.