Patents by Inventor Huang-Yu Chen
Huang-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11200364Abstract: A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.Type: GrantFiled: September 25, 2019Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia Cheng Chen, Ching-Fang Chen, Huang-Yu Chen, Jen Ping Hsu
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Publication number: 20210133384Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.Type: ApplicationFiled: January 17, 2021Publication date: May 6, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
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Publication number: 20210089630Abstract: A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.Type: ApplicationFiled: September 25, 2019Publication date: March 25, 2021Inventors: CHIA CHENG CHEN, CHING-FANG CHEN, HUANG-YU CHEN, JEN PING HSU
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Patent number: 10922466Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.Type: GrantFiled: December 5, 2018Date of Patent: February 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
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Publication number: 20200081348Abstract: A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen
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Patent number: 10509322Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.Type: GrantFiled: June 22, 2016Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen
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Publication number: 20190108302Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.Type: ApplicationFiled: December 5, 2018Publication date: April 11, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
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Patent number: 10162925Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.Type: GrantFiled: September 18, 2015Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
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Patent number: 9893009Abstract: In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance.Type: GrantFiled: January 10, 2014Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Huang-Yu Chen, Chi-Yeh Yu, Chung-Hsing Wang
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Patent number: 9754073Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: GrantFiled: August 15, 2016Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 9747402Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.Type: GrantFiled: December 9, 2014Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
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Patent number: 9640450Abstract: A method for reducing light-induced-degradation in manufacturing a solar cell, includes the steps of: (a) irradiating the solar cell with an irradiance; (b) maintaining the solar cell within a temperature range; (c) removing the solar cell away from the irradiance of step (a) after a time; and (d) determining the irradiance, the temperature range, and the time such that the LID is optimally below a predetermined LID.Type: GrantFiled: October 23, 2015Date of Patent: May 2, 2017Assignee: MOTECH INDUSTRIES INC.Inventors: Kuang-Yang Kuo, Wei-Lun Lu, Huang-Yu Chen, Chien-Chun Wang, Yu-Pan Pai
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Publication number: 20170117197Abstract: A method for reducing light-induced-degradation in manufacturing a solar cell, comprises the steps of: (a) irradiating the solar cell with an irradiance; (b) maintaining the solar cell within a temperature range; (c) removing the solar cell away from the irradiance of step (a) after a time; and (d) determining the irradiance, the temperature range, and the time such that the LID is optimally below a predetermined LID.Type: ApplicationFiled: October 23, 2015Publication date: April 27, 2017Inventors: Kuang-Yang KUO, Wei-Lun LU, Huang-Yu CHEN, Chien-Chun WANG, Yu-Pan PAI
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Publication number: 20170083654Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.Type: ApplicationFiled: September 18, 2015Publication date: March 23, 2017Inventors: Yi-Lin CHUANG, Huang-Yu CHEN, Yun-Han LEE
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Patent number: 9594866Abstract: A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.Type: GrantFiled: November 19, 2012Date of Patent: March 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20160350473Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20160320706Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.Type: ApplicationFiled: June 22, 2016Publication date: November 3, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Hsiung HSU, Huang-Yu CHEN, Tsong-Hua OU, Wen-Hao CHEN
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Patent number: 9471742Abstract: A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.Type: GrantFiled: October 24, 2014Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
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Patent number: 9418196Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.Type: GrantFiled: January 16, 2015Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 9384307Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.Type: GrantFiled: August 20, 2013Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Chung-Hsing Wang