Patents by Inventor Huang-Yu Chen
Huang-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8898600Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.Type: GrantFiled: July 15, 2013Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 8875067Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.Type: GrantFiled: May 14, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Wen-Hao Chen
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Publication number: 20140298284Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.Type: ApplicationFiled: June 16, 2014Publication date: October 2, 2014Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
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Patent number: 8850368Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.Type: GrantFiled: January 30, 2013Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng
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Publication number: 20140282287Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.Type: ApplicationFiled: May 14, 2013Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Yuan-Te Hou, Wen-Hao Chen
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Publication number: 20140259658Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.Type: ApplicationFiled: June 24, 2013Publication date: September 18, 2014Inventors: Chin-Hsiung HSU, Huang-Yu CHEN, Tsong-Hua OU, Wen-Hao CHEN
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Publication number: 20140282306Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.Type: ApplicationFiled: July 15, 2013Publication date: September 18, 2014Inventors: Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20140237435Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: ApplicationFiled: May 1, 2014Publication date: August 21, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu CHEN, Tsong-Hua OU, Ken-Hsien HSIEH, Chin-Hsiung HSU
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Patent number: 8813016Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.Type: GrantFiled: January 28, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
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Patent number: 8799834Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant.Type: GrantFiled: January 30, 2013Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Huang-Yu Chen, Li-Chun Tien, Ken-Hsien Hsieh, Jhih-Jian Wang, Chin-Chang Hsu, Chin-Hsiung Hsu, Pin-Dai Sue, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 8756552Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.Type: GrantFiled: January 28, 2013Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Hsiung Hsu, Huang-Yu Chen, Li-Chun Tien, Lee-Chung Lu, Hui-Zhong Zhuang, Cheng-I Huang, Chung-Hsing Wang, Yi-Kan Cheng
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Patent number: 8745556Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: GrantFiled: June 28, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Tsong-Hua Ou, Ken-Hsien Hsieh, Chin-Hsiung Hsu
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Patent number: 8694945Abstract: The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.Type: GrantFiled: December 20, 2011Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hsing Wang, King-Ho Tam, Huang-Yu Chen
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Patent number: 8683392Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.Type: GrantFiled: July 21, 2011Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ken-Hsien Hsieh, Huang-Yu Chen, Jhih-Jian Wang, Cheng Kun Tsai, Tsong-Hua Ou, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20140059504Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.Type: ApplicationFiled: October 31, 2013Publication date: February 27, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu CHEN, Yuan-Te HOU, Chung-Min FU, Chung-Hsing WANG, Wen-Hao CHEN, Yi-Kan CHENG
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Publication number: 20140053118Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.Type: ApplicationFiled: October 28, 2013Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu CHEN, Chin-Hsiung HSU, Wen-Hao CHEN, Chung-Hsing WANG
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Publication number: 20140007026Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huang-Yu CHEN, Tsong-Hua OU, Ken-Hsien HSIEH, Chin-Hsiung HSU
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Publication number: 20130339911Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung HSU, Huang-Yu CHEN, Chung-Hsing WANG
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Patent number: 8601409Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.Type: GrantFiled: July 12, 2012Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.Inventors: Huang-Yu Chen, Chin-Hsiung Hsu, Wen-Hao Chen, Chung-Hsing Wang
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Patent number: 8601408Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.Type: GrantFiled: October 10, 2011Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng