Patents by Inventor HUANG YU

HUANG YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8273679
    Abstract: A porous catalyst includes at least one noble nano-metal particle, an oxide for forming porous structures, and a carrier material for supporting the oxide and the at least one noble nano-metal particle. The porous catalyst shows a large electrochemical surface area and a highly conductive ability. Further, the noble nano-metal particles are separated on the oxides uniformly, and the oxide of the catalyst forms a porous structure to provide a large electrochemical surface area. The porous catalyst provides excellent proton/electron transfer ability and increases the reaction rate.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 25, 2012
    Assignee: National Central University
    Inventors: Po-Jen Chu, Jhuh-Wei Yang, Chieh-Chun Chang, Huang-Yu Lee
  • Patent number: 8246192
    Abstract: A portable electronic device includes a housing; a touch tip portion fixed to one end of the housing; a cover fixed to the other end of the housing; a laser unit disposed in the housing adjacent to the touch tip portion; a rechargeable battery disposed in the housing electrically connected to the laser unit; and a first charging connecting portion and a second charging connecting portion positioned on an outer surface of the housing apart. The first charging connecting portion includes a first connecting end electrically connected to a negative electrode of an external power and a second connecting end electrically connected to the positive electrode of the rechargeable battery. The second charging connecting portion includes a first connecting end electrically connected to a positive electrode of an external power and a second connecting end electrically connected to the negative electrode of the rechargeable battery.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 21, 2012
    Assignees: Shenzhen Futaihong Precision Industry Co., Ltd., Chi Mei Communication Systems, Inc.
    Inventor: Huang-Yu Xu
  • Patent number: 8239806
    Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng, Lee-Chung Lu
  • Patent number: 8211807
    Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Ken-Hsien Hsieh, Tsong-Hua Ou, Fang-Yu Fan, Yuan-Te Hou, Ming-Feng Shieh, Ru-Gun Liu, Lee-Chung Lu
  • Publication number: 20120167021
    Abstract: A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell.
    Type: Application
    Filed: April 11, 2011
    Publication date: June 28, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Ken-Hsien Hsieh, Ru-Gun Liu, Lee-Chung Lu
  • Publication number: 20120131528
    Abstract: A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Lee-Chung Lu, Ru-Gun Liu, Ken-Hsien Hsieh, Lee Fung Song, Wen-Chun Huang, Li-Chun Tien
  • Publication number: 20120091592
    Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Ken-Hsien Hsieh, Tsong-Hua Ou, Fang-Yu Fan, Yuan-Te Hou, Ming-Feng Shieh, Ru-Gun Liu, Lee-Chung Lu
  • Publication number: 20120089275
    Abstract: A simulation transmitter for remote operated vehicles (STROV) is disclosed for allowing users in the toy and hobby industry to realistically simulate, everyday driving experiences and implement them into any remote-controlled vehicle. The STROV system remotely operates land, air and sea remote controlled hobby vehicles, boats and planes. It includes a steering wheel, a separate hand-operated throttle and brake control and a separate foot-operated throttle and brake control.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 12, 2012
    Inventors: Lee Yao-Chang, Huang Yu-Chien
  • Patent number: 8149016
    Abstract: An interface circuit electronically connects a processor and a card reader. The interface circuit includes a clock circuit, a reset circuit, and an I/O circuit. The clock circuit may transmit a clock signal transmitted from the processor to the card reader, and includes a first bipolar junction transistor (BJT). The reset circuit may transmit a reset signal transmitted from the processor to the card reader, and includes a second BJT. The I/O circuit may transmit data transmitted from the processor to the card reader, and includes a third BJT and a fourth BJT.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 3, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Huang-Yu Chiang
  • Publication number: 20120077672
    Abstract: A porous catalyst includes at least one noble nano-metal particle, an oxide for forming porous structures, and a carrier material for supporting the oxide and the at least one noble nano-metal particle. The porous catalyst shows a large electrochemical surface area and a highly conductive ability. Further, the noble nano-metal particles are separated on the oxides uniformly, and the oxide of the catalyst forms a porous structure to provide a large electrochemical surface area. The porous catalyst provides excellent proton/electron transfer ability and increases the reaction rate.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Po-Jen Chu, Jhih-Wei Yang, Chieh-Chun Chang, Huang-Yu Lee
  • Publication number: 20120038389
    Abstract: An interface circuit electronically connects a processor and a card reader. The interface circuit includes a clock circuit, a reset circuit, and an I/O circuit. The clock circuit may transmit a clock signal transmitted from the processor to the card reader, and includes a first bipolar junction transistor (BJT). The reset circuit may transmit a reset signal transmitted from the processor to the card reader, and includes a second BJT. The I/O circuit may transmit data transmitted from the processor to the card reader, and includes a third BJT and a fourth BJT.
    Type: Application
    Filed: December 7, 2010
    Publication date: February 16, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: HUANG-YU CHIANG
  • Patent number: 8103499
    Abstract: To enter Chinese text, a user enters the corresponding phonetic spelling via telephone style keypad. Some or all keys represent multiple phonetic letters. In disambiguating entered key presses to yield a valid phonetic spelling, a computer divides the key presses into segments, while still preserving key press order. Each segment must correspond to an entry in a dictionary of Chinese characters, character phrases, and/or character components such as radicals or other predetermined stroke groupings. Upon arrival of a new key press that cannot form a valid entry when appended to the current segment, key presses are incrementally reallocated from the previous segment. As for already-resolved segments occurring prior to the previous and current segments, these are left intact. After each shifting attempt, the computer reinterprets key presses of the last two segments, and accepts the new segmentation if the segments form valid dictionary entries.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: January 24, 2012
    Assignee: Tegic Communications, Inc.
    Inventors: Jenny Huang-Yu Lai, Jianchao Wu
  • Publication number: 20110308961
    Abstract: A pattern processing method of a workpiece surface includes at least the following steps. A first anodized process is performed to a workpiece, wherein a surface of the workpiece includes at least one flat portion and at least one curved portion. A patterned film including a releasable substrate and an acid-base resistant ink layer disposed thereon is provided, wherein a surface of the releasable substrate on which the acid-base resistant ink layer is disposed faces the workpiece. A force is applied to an edge of the patterned film to adhere the patterned film the workpiece smoothly, so as to transfer a pattern of the acid-base resistant ink layer to the workpiece. The releasable substrate is removed. The workpiece is etched and the acid-base resistant ink layer is removed; and a second anodized process is performed to form a dichromatic anode three-dimensional texture.
    Type: Application
    Filed: September 20, 2010
    Publication date: December 22, 2011
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Pei-Yi Chu, Chang-Kai Liu, Chun-Huang Yu
  • Publication number: 20110296360
    Abstract: A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dio WANG, Ken-Hsien HSIEH, Huang-Yu CHEN, Li-Chun TIEN, Ru-Gun LIU, Lee-Chung LU
  • Publication number: 20110193234
    Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
  • Publication number: 20110166753
    Abstract: The present invention relates to a walking assistance device with detection function, which includes a movable frame, a power transmission device mounted under the frame, a detachable power unit mounted on the frame, at least one signal transmitter and at least one signal receiver for detecting the distances from a first portion and a second portion on the user's body to a correspond position of the frame respectively. According to the distances detected, a control unit sends signals to the power transmission device to maintain the distance between the user and the frame within a preset range, therefore to provide supporting forces when the user needs.
    Type: Application
    Filed: May 21, 2010
    Publication date: July 7, 2011
    Inventors: Chung-huang YU, Chih-wei Chien
  • Publication number: 20110119648
    Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
    Type: Application
    Filed: December 30, 2009
    Publication date: May 19, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng, Lee-Chung Lu
  • Publication number: 20110077562
    Abstract: The invention discloses a gait training device for people with walking disability. Using motors and six-bar linkage mechanism, the invention can guide users' ankles to follow preferred gait trajectories, and thus help people with walking disability practice correct gaits.
    Type: Application
    Filed: February 24, 2010
    Publication date: March 31, 2011
    Applicant: National Taiwan University
    Inventors: Fu-cheng Wang, Chung-Huang Yu, Nai-Chung Chang, Tai-yu Chou
  • Publication number: 20110072405
    Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
    Type: Application
    Filed: July 7, 2010
    Publication date: March 24, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu
  • Publication number: 20110003254
    Abstract: A layout decomposition method, applicable to a double pattern lithography, includes the steps of: putting at least a stitch on each of a plurality of sub-patterns of an initial layout pattern at preset intervals to thereby divide the each of the plurality of sub-patterns into a plurality of unit blocks each selectively labeled as a first region or a second region such that the first region and the second region in same said sub-pattern alternate, wherein any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, are labeled as the first region and the second region, respectively; reducing the stitches of any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, so as to generate a first layout pattern having a minimum number of stitches; and reducing the stitches of any two contiguous ones of said unit blocks of each of said sub-patterns in the first layout pattern, so as to generate a se
    Type: Application
    Filed: July 2, 2010
    Publication date: January 6, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Yao-Wen Chang, Huang-Yu Chen