Abstract: A signal synthesis circuit synthesizes luma signals and chroma signals output by a video signal source, to output composite video broadcast signals (CVBS). The signal synthesis circuit includes a first gain adjusting unit, a delay unit, and a second gain adjusting unit. The first gain adjusting unit receives and adjusts the gain of the luma signals from the video signal source, and the delay unit delays phases of the luma signals output by the first gain adjusting unit. The second gain adjusting unit receives and adjusts the gain of the chroma signals from the video signal source so that the luma signals output by the delay unit and the chroma signals output by the second gain adjusting unit can be synthesized into the CVBS.

Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract: Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: A portable electronic device adapted to be detachably connected to a cradle having a containing cavity is provided, wherein an inner wall of the containing cavity has a recess. The portable electronic device includes a body and a locking-and-releasing mechanism disposed in the body and including a driving unit and a latch. The driving unit is disposed in the body. The latch is connected to the driving unit and suitable for being driven by the driving unit to protrude out of the body or hide in the body. When the portable electronic device is disposed in the containing cavity, the driving unit drives the latch to protrude out of the body and be engaged with the recess. When the portable electronic device is going to be detached from the containing cavity, the driving unit drives the latch to be disengaged from the recess and move back in the body.

Abstract: An electronic device including a first body, an input module and a functional element is provided. The input module is movably disposed on the first body and adapted to be moved between a first position and a second position. The functional element is disposed on the input module. When the input module is located at the first position, the functional element is concealed in the first body. When the input module is located at the second position, the functional element is exposed outside the first body.

Abstract: A portable quantification apparatus for assessing joint accessory movement is disclosed in the present invention. The apparatus includes a reference module, a movement module, a sliding module and a displacement sensor module. The reference module has a first probe and a first force sensor. The movement module has a second probe and a second force sensor. The sliding module is disposed between the reference module and the movement module which allows the movement module to slide alongside with the reference module. When a patient is under a test, the first probe is against one of two adjacent bones of a joint, while the second probe is against the other adjacent bone. The first force sensor and the second force sensor sense a first force and a second force applying to the reference module and the movement module respectively. The displacement sensor module measures the displacement of the movement module over the reference module.

Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

Abstract: In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance.

Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

Abstract: A portable electronic device includes a cover, a main body, a first bracket, a second bracket and a rotary shaft. The main body includes a top surface, a bottom surface opposite to the top surface, and a guiding groove disposed on the top surface. One end of the first bracket pivots to the cover, and the other of the first bracket is slidable in the guiding groove. One end of the second bracket pivots to the cover. The rotary shaft pivots to the other of the second bracket and the main body to allow the second bracket to rotate about an axis of rotation relative to the main body. An orthographic projection of the guiding groove on the bottom surface of the main body and an orthographic projection of the rotary shaft on the bottom surface of the main body are overlapped with each other.

Abstract: An electronic device includes a first body and a second body. The first body includes a first main body and a first magnetic element fixed in the first main body. The second body includes a second main body, a supporting unit, a second magnetic element, and a third magnetic element. The second main body is adapted to hold the first body. The supporting unit is pivoted to the second main body. The second magnetic element is fixed in the second main body. The third magnetic element is slidably configured in the second main body to restrict a rotation of the supporting unit relative to the second main body. When the first body leans against the second main body, the third magnetic element is subject to a magnetic attraction force from the first magnetic element and escapes from the supporting unit, so that the supporting unit supports the first body.

Abstract: A LDMOS structure including a semiconductor substrate, a drain region, a lightly doped drain (LDD) region, a source region and a gate structure is provided. The substrate has a trench. The drain region is formed in the semiconductor substrate under the trench. A LDD region is formed in the semiconductor substrate at a sidewall of the trench. The source region is formed in the semiconductor substrate. The gate structure is formed on a surface of the semiconductor substrate above the LDD region between the drain region and the source region. A method for manufacturing the LDMOS structure is also provided.

Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.

Abstract: A method of designing integrated circuits includes forming a restricted cell library from a first cell library by selecting only those cells in the first cell library that are most efficient according to predetermined efficiency criteria and executing an integrated circuit design operation in an electronic design automation program while directing the electronic design automation program to make cell selections exclusively from the restricted cell library. The integrated circuit design operation is one that can be directed to make cell selections from any of the cells in the first cell library without changing its essential purpose. The method improves QoR for the resulting circuit design.

Abstract: A base assembly of an office chair includes a mounting member, multiple extensions and a bottom disk. The mounting member has multiple installation slots located evenly along the periphery of the mounting member. Each extension has a connection member at the first end thereof so as to be engaged with the installation slot corresponding thereto. The bottom disk is located at the underside of the first end of each of the extensions and has multiple holes and a central hole. Bolts extend through the holes and are connected to the underside of the mounting member to position the first ends of the extensions.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.