Abstract: An electric walking assistance device is provided. The electric walking assistance device comprises: a support member comprising at least one movable component; a user area where a user can stand, wherein the user area is a ground area adjacent to the support member. The electric walking assistance device further comprises at least one gait monitoring module and at least one gait assisting module, wherein the at least one gait monitoring module and the at least one gait assisting module are on the support member, the user's body, an arbitrary point within the detection range covering a range of user activities or any combinations thereof.

Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

Abstract: In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance.

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Abstract: An electric walking aid and control method thereof are disclosed. A location of the electric walking aid, and a distance between the electric walking aid and the user, are dynamically controlled and adjusted to provide the user with static and dynamic support function, so as to support the user under static and dynamic situation of interaction between walk and stand, during the walking training process.

Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract: A low-loss few-mode fiber relates to the technical field of optical communications and related sensing devices, and includes, from inside to outside, a core layer (1), a fluorine-doped quartz inner cladding (2), a fluorine-doped quartz second core layer (3), a fluorine-doped quartz depressed cladding (4) and a fluorine-doped quartz outer cladding (5); germanium element is not doped within the core layer (1), the refractive index of the core layer (1) is in gradient distribution, and the distribution is a power-exponent distribution; the maximum value of difference in relative refractive index between the core layer (1) and the fluorine-doped quartz inner cladding (2) is 0.3% to 0.9%; the relative refractive index difference of the fluorine-doped quartz inner cladding (2) with respect to synthetic quartz is ?0.3% to ?0.5%; the difference in relative refractive index between the fluorine-doped quartz second core layer (3) and the fluorine-doped quartz inner cladding (2) is 0.05% to 0.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Abstract: A high voltage transistor includes a substrate, a well which is disposed within the substrate, a gate disposed on the well, a gate dielectric layer disposed between the well and the gate, two drift regions respectively disposed in the well at two sides of the gate, two source/drain regions respectively disposed within each drift region, wherein a width of the gate dielectric layer is smaller than a width of the source/drain region, and two isolation elements respectively disposed within each drift region

Abstract: A method for reducing light-induced-degradation in manufacturing a solar cell, includes the steps of: (a) irradiating the solar cell with an irradiance; (b) maintaining the solar cell within a temperature range; (c) removing the solar cell away from the irradiance of step (a) after a time; and (d) determining the irradiance, the temperature range, and the time such that the LID is optimally below a predetermined LID.

Abstract: A method for reducing light-induced-degradation in manufacturing a solar cell, comprises the steps of: (a) irradiating the solar cell with an irradiance; (b) maintaining the solar cell within a temperature range; (c) removing the solar cell away from the irradiance of step (a) after a time; and (d) determining the irradiance, the temperature range, and the time such that the LID is optimally below a predetermined LID.

Abstract: A low-loss few-mode fiber relates to the technical field of optical communications and related sensing devices, and includes, from inside to outside, a core layer (1), a fluorine-doped quartz inner cladding (2), a fluorine-doped quartz second core layer (3), a fluorine-doped quartz depressed cladding (4) and a fluorine-doped quartz outer cladding (5); germanium element is not doped within the core layer (1), the refractive index of the core layer (1) is in gradient distribution, and the distribution is a power-exponent distribution; the maximum value of difference in relative refractive index between the core layer (1) and the fluorine-doped quartz inner cladding (2) is 0.3% to 0.9%; the relative refractive index difference of the fluorine-doped quartz inner cladding (2) with respect to synthetic quartz is ?0.3% to ?0.5%; the difference in relative refractive index between the fluorine-doped quartz second core layer (3) and the fluorine-doped quartz inner cladding (2) is 0.05% to 0.

Abstract: Provided is a semiconductor structure including a substrate, a first gate, a second gate, a third gate and an inter-gate dielectric layer. The substrate has a first area and a second area, and the first surface of the first area is lower than the second surface of the second area. The first gate is disposed on the first surface of the first area. The second gate includes metal and is disposed on the first gate. The inter-gate dielectric layer is disposed between the first and second gates. The third gate includes metal and is disposed on the second surface of the second area. A method of foaming a semiconductor structure is further provided.

Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.

Abstract: A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Abstract: A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; using a first patterned mask to form a gate dielectric layer on the substrate; removing the first patterned mask; removing part of the gate dielectric layer; and forming a shallow trench isolation (STI) adjacent to two sides of the gate dielectric layer.