Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate i

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract: The invention provides a vertically adjustable chemical mechanical polishing head having a pivot mechanism and method for use thereof.

Abstract: In one aspect, the invention provides a method for planarizing a circular disc-type semiconductor wafer or other substrate. The method includes the steps of pressing a retaining ring surrounding the wafer against a polishing pad at a first pressure; pressing a first peripheral edge portion of the wafer against the polishing pad with a second pressure; and pressing a second portion of the wafer interior to the peripheral edge portion against the polishing pad with a third pressure. The second pressure may be provided through a mechanical member in contact with the peripheral edge portion; and the second pressure may be a pneumatic pressure against a backside surface of the wafer. Desirably, the pneumatic pressure is exerted through a resilient membrane, or is exerted by gas pressing directly against at least a portion of the wafer backside surface.

Abstract: The invention provides a chemical mechanical polishing and pad dressing method based on differing the rotational of a pad dresser, head, and/or polishing pad to improve center removal slow profiling.

Abstract: In one aspect, the invention provides a method for planarizing a circular disc-type semiconductor wafer or other substrate. The method includes the steps of pressing a retaining ring surrounding the wafer against a polishing pad at a first pressure; pressing a first peripheral edge portion of the wafer against the polishing pad with a second pressure; and pressing a second portion of the wafer interior to the peripheral edge portion against the polishing pad with a third pressure. The second pressure may be provided through a mechanical member in contact with the peripheral edge portion; and the second pressure may be a pneumatic pressure against a backside surface of the wafer. Desirably, the pneumatic pressure is exerted through a resilient membrane, or is exerted by gas pressing directly against at least a portion of the wafer backside surface.

Abstract: A chemical mechanical processing apparatus includes a polishing pad capable of polishing a substrate; a stepped retaining having an inner side, a bottom side, and an open region, the open region extending radially outward from the inner side and upward from the bottom side, the open region providing space for pad rebound, the open region further having a plurality of tips to hold a substrate in position during rotation of the substrate against the polishing pad, the stepped retaining ring capable of rotating the substrate against the polishing pad; and a dispenser capable of dispensing a slurry onto the pad.

Abstract: The system includes a polishing pad, a pad height sensor; a window; and a window raising mechanism. The polishing pad has an aperture with the window vertically moveable therein. The pad height sensor is positioned above the polishing pad and measures the vertical position of the pad before polishing. The window raising mechanism adjusts the vertical position of the window based on information from the pad height sensor. An endpoint measurement sensor can be disposed beneath the window for in-situ measurement of the polishing process.

Abstract: A system (100) and method for polishing and planarizing a substrate (105) is provided that reduces non-uniformities in the removal of material from the edge of the substrate due to a rebound effect. In one embodiment system (100) includes a polishing head (140) having a carrier (155), a subcarrier (160) carried by the carrier and adapted to hold the substrate during a polishing operation, and a retaining ring (170) having an inner edge (220) disposed about the subcarrier. A lower surface (210) of the retaining ring (170) is in contact with a polishing surface (125) during the polishing operation, and has at least one annular recess (215) formed therein to enable the polishing surface compressed under the retaining ring to rebound into the annular recess, thereby reducing the rebound effect and inhibiting non-planar polishing of the surface of the substrate (105).

Abstract: The system includes a polishing pad, a pad height sensor; a window; and a window raising mechanism. The polishing pad has an aperture with the window vertically moveable therein. The pad height sensor is positioned above the polishing pad and measures the vertical position of the pad before polishing. The window raising mechanism adjusts the vertical position of the window based on information from the pad height sensor. An endpoint measurement sensor can be disposed beneath the window for in-situ measurement of the polishing process.

Abstract: The invention provides a vertically adjustable chemical mechanical polishing head having a pivot mechanism and method for use thereof.