Patents by Inventor Hugh E. Stroupe

Hugh E. Stroupe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8053371
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: November 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Patent number: 7449368
    Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: November 11, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Hugh E. Stroupe
  • Patent number: 7307353
    Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: December 11, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Hugh E. Stroupe
  • Patent number: 7244681
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Renee Zahorik, legal representative, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Russell C. Zahorik, deceased
  • Patent number: 7135763
    Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: November 14, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Hugh E. Stroupe
  • Patent number: 6889698
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Patent number: 6882032
    Abstract: A semiconductor assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Hugh E. Stroupe
  • Patent number: 6828227
    Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed resilient flexible material member contacting the wafer.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: December 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Lynn J. Carroll
  • Publication number: 20040038543
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Application
    Filed: August 25, 2003
    Publication date: February 26, 2004
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Renee Zahorik
  • Patent number: 6693034
    Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed flexible planar interface material contacting the deformable material.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Brian F. Gordon
  • Patent number: 6656402
    Abstract: In connection with wafer planarization, an apparatus for forming a layer of material having a substantially uniform thickness and substantially parallel first and second major surfaces includes a pair of pressing elements and a stop. Each of the pair of pressing elements has a flat pressing surface. The pressing surfaces are opposed to one another and operable to compress a quantity of the material therebetween. The stop is positioned at least partially between the pressing surfaces and has a thickness substantially equal to the desired uniform thickness of the layer. The stop is positioned to establish a spacing between the flat pressing surfaces that is substantially equal to the thickness of the stop and thereby to the desired uniform thickness of the layer when the pressing elements engage the stop.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: December 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Brian F. Gordon
  • Patent number: 6653722
    Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed resilient flexible material member contacting the wafer.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: November 25, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Lynn J. Carroll
  • Patent number: 6645345
    Abstract: In connection with wafer planarization, an apparatus for forming a layer of material having a substantially uniform thickness and substantially parallel first and second major surfaces includes a pair of pressing elements and a stop. Each of the pair of pressing elements has a flat pressing surface. The pressing surfaces are opposed to one another and operable to compress a quantity of the material therebetween. The stop is positioned at least partially between the pressing surfaces and has a thickness substantially equal to the desired uniform thickness of the layer. The stop is positioned to establish a spacing between the flat pressing surfaces that is substantially equal to the thickness of the stop and thereby to the desired uniform thickness of the layer when the pressing elements engage the stop.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: November 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Brian F. Gordon
  • Patent number: 6624089
    Abstract: In connection with wafer planarization, an apparatus for forming a layer of material having a substantially uniform thickness and substantially parallel first and second major surfaces includes a pair of pressing elements and a stop. Each of the pair of pressing elements has a flat pressing surface. The pressing surfaces are opposed to one another and operable to compress a quantity of the material therebetween. The stop is positioned at least partially between the pressing surfaces and has a thickness substantially equal to the desired uniform thickness of the layer. The stop is positioned to establish a spacing between the flat pressing surfaces that is substantially equal to the thickness of the stop and thereby to the desired uniform thickness of the layer when the pressing elements engage the stop.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: September 23, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Brian F. Gordon
  • Patent number: 6610610
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: August 26, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Publication number: 20030121538
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Application
    Filed: February 14, 2003
    Publication date: July 3, 2003
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Publication number: 20030104691
    Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed resilient flexible material member contacting the wafer.
    Type: Application
    Filed: November 6, 2002
    Publication date: June 5, 2003
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Lynn J. Carroll
  • Patent number: 6555897
    Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 29, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Hugh E. Stroupe
  • Patent number: 6530113
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: March 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Publication number: 20030034490
    Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.
    Type: Application
    Filed: October 18, 2002
    Publication date: February 20, 2003
    Inventor: Hugh E. Stroupe