Abstract: A self-describing data format capable of carrying payload information, such as Tuxedo payload information, as well as filter information. The data format can allow for expression of some or all of Tuxedo Typed Buffers, including STRING, CARRAY, MBSTRING, VIEW, VIEW32, FML, and FML32. The data format is also capable of supporting nesting and error-checking. The proposal of user payload collection can allow customers to siphon off user/payload data to be used in applications, such as Business Intelligence applications, without the need for additional information to be passed with the payload data.

Abstract: A semiconductor structure is disclosed, including a first conductive line and a first power rail and a first transistor structure arranged between the first conductive line and the first power rail. The first conductive line and the first power rail are separated from each other in a first direction. The first transistor structure includes a first active region coupled to the first conductive line by a first via; a second active region coupled to the first power rail by a second via; and a first gate structure interposed between the first active region and the second active region, and configured to receive a first control signal. The first transistor structure transmits a signal between the first conductive line and the first power rail in response to the first control signal.

Abstract: A route plotting method includes: displaying an electronic map; determining multiple position points in the electronic map, where longitude coordinates of the multiple position points fall within a first longitude coordinate range; converting a project longitude coordinate to a target longitude coordinate range in response to that the multiple position points meet a conversion condition; where the conversion condition includes: an absolute value of a difference between longitude coordinates of adjacent position points is greater than a first value, the first value being a maximum value within the first longitude coordinate range; and the project longitude coordinate is a longitude coordinate in the longitude coordinates of the multiple position points that does not fall within the target longitude coordinate range; and plotting, in order of converted longitude coordinates, a route formed by connecting the multiple position points in the electronic map.

Abstract: Disclosed herein is a formulation that includes a hybrid composite material, at least one photopolymerizable monomer, one or both of a free radical photoinitiator and an oxidizable radical co-producer. The hybrid composite material is formed from an organic semiconducting material and a conductive material, where the organic semiconducting material is bonded to the conductive material. In specific embodiments, the hybrid composite material is polydopamine/multiwalled carbon nanotubes (PDA/MWCNTs) hybrid composite or polydopamine/gallium zinc oxide (PDA/GZO) hybrid composite. Also disclosed herein are a method of initiating and/or sensitizing photopolymerization and method of additive manufacture via photopolymerization using said formulation.

Abstract: The laser device includes a substrate, a laser element disposed on the substrate for emitting a laser light ray, a light guide member disposed on the substrate, and a wavelength conversion layer. The light guide member is light-transmissible and thermally conductive, and has at least one reflection surface for reflecting the laser light ray from the laser element so as to change travelling direction of the laser light ray. The wavelength conversion layer converts wavelength of the laser light ray from the light guide member to result in a laser beam, and contacts the light guide member so that heat from the wavelength conversion layer is transferred to the substrate through the light guide member.

Abstract: A polishing system includes a platen to hold a polishing pad, a carrier head to hold a substrate against the polishing pad, a conditioner including a conditioner head to hold a conditioner disk against the polishing pad, a motor to move the conditioner head laterally movable relative to the platen, a conditioning disk cleaning station positioned adjacent the platen to clean the conditioning disk, and a controller configured to cause the motor to, during polishing of the substrate, move the conditioner head back and forth between a first position with the conditioner head over the polishing pad and a second position with the conditioner head in the conditioner disk cleaning station.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

Abstract: Embodiments of the present disclosure generally relate to silicon carbide coated base substrates, silicon carbide substrates thereof, and methods for forming silicon carbide coated base substrates. In some embodiments, a method includes introducing a first silicon-containing precursor to a process chamber at a first temperature of about 800° C. to less than 1,000° C. to form a first silicon carbide layer on a base substrate. The method includes introducing a second silicon-containing precursor, that is the same or different than the first silicon-containing precursor, to the process chamber at a second temperature of about 1,000° C. to about 1,400° C. to form a second silicon carbide layer on the first silicon carbide layer.

Abstract: The present disclosure provides liver-specific Wnt signal enhancing molecules, and related methods of using these molecules to increase Wnt signaling in liver tissues and treat liver diseases and disorders.

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Abstract: A manufacturing method of tape includes the steps of providing a tape including substrate units, providing a die device and a cutting and/or pressing process. Each of the substrate units includes a carrier, a circuit layer, an adhesive and a heat spreader, the heat spreader is attached onto the carrier by the adhesive. In the cutting and/or pressing process, the die device is provided to press the tape to generate separation protrusions on the heat spreader and allow the separation protrusions to protrude from a heat dissipation surface of the heat spreader. When rolling the tape, the separation protrusions can separate the stacked substrate units to prevent the adhesive from being squeezed out to contaminate the tape.

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.