Abstract: Disclosed herein is a polymeric product formed from a cured polymeric material that comprises a repeating unit derived from a monomer according to formula I or formula II: where Ra, Rb and R1 to R6 are defined herein. Also disclosed herein are the monomers according to formula I and II, as well as formulations comprising said monomers.

Abstract: A connector module is adapted to be disposed in a casing including a casing opening. The connector module includes a connector shell, an elastic rib, a connection terminal, a first and a second conductive layer. The connector shell includes a front side and a first opening. The first opening is aligned with the casing opening. The elastic rib is disposed and protrudes from the front side. The elastic rib surrounds the first opening. The connection terminal is disposed in the connector shell and exposed to the first opening. The first conductive layer is coated on the front side and the elastic rib, and contacts with the casing. The second conductive layer is laid on a side of the first conductive layer opposite to the front side and includes a second opening. The first opening and the elastic rib coated with the first conductive layer are exposed to the second opening.

Abstract: An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: Disclosed herein are methods for detecting methylation in cell-free polynucleotides and methods for detecting the presence of cancer in a subject.

Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Abstract: A method for measuring disaster resilience of urban public services includes the following steps: constructing a residence-service-transportation space network under normal conditions; removing, through disaster simulation, failed road segments and function nodes to construct a damaged residence-service-transportation space network; calculating a per capita accessible public service of each residential node to represent network performance; calculating a change rate of the per capita accessible public service level before and after the disaster; and drawing a relation curve between the change rate and the disaster intensity to measure the disaster resilience of the urban public services.

Abstract: A self-describing data format capable of carrying payload information, such as Tuxedo payload information, as well as filter information. The data format can allow for expression of some or all of Tuxedo Typed Buffers, including STRING, CARRAY, MBSTRING, VIEW, VIEW32, FML, and FML32. The data format is also capable of supporting nesting and error-checking. The proposal of user payload collection can allow customers to siphon off user/payload data to be used in applications, such as Business Intelligence applications, without the need for additional information to be passed with the payload data.

Abstract: A semiconductor structure is disclosed, including a first conductive line and a first power rail and a first transistor structure arranged between the first conductive line and the first power rail. The first conductive line and the first power rail are separated from each other in a first direction. The first transistor structure includes a first active region coupled to the first conductive line by a first via; a second active region coupled to the first power rail by a second via; and a first gate structure interposed between the first active region and the second active region, and configured to receive a first control signal. The first transistor structure transmits a signal between the first conductive line and the first power rail in response to the first control signal.

Abstract: A route plotting method includes: displaying an electronic map; determining multiple position points in the electronic map, where longitude coordinates of the multiple position points fall within a first longitude coordinate range; converting a project longitude coordinate to a target longitude coordinate range in response to that the multiple position points meet a conversion condition; where the conversion condition includes: an absolute value of a difference between longitude coordinates of adjacent position points is greater than a first value, the first value being a maximum value within the first longitude coordinate range; and the project longitude coordinate is a longitude coordinate in the longitude coordinates of the multiple position points that does not fall within the target longitude coordinate range; and plotting, in order of converted longitude coordinates, a route formed by connecting the multiple position points in the electronic map.

Abstract: Disclosed herein is a formulation that includes a hybrid composite material, at least one photopolymerizable monomer, one or both of a free radical photoinitiator and an oxidizable radical co-producer. The hybrid composite material is formed from an organic semiconducting material and a conductive material, where the organic semiconducting material is bonded to the conductive material. In specific embodiments, the hybrid composite material is polydopamine/multiwalled carbon nanotubes (PDA/MWCNTs) hybrid composite or polydopamine/gallium zinc oxide (PDA/GZO) hybrid composite. Also disclosed herein are a method of initiating and/or sensitizing photopolymerization and method of additive manufacture via photopolymerization using said formulation.

Abstract: The laser device includes a substrate, a laser element disposed on the substrate for emitting a laser light ray, a light guide member disposed on the substrate, and a wavelength conversion layer. The light guide member is light-transmissible and thermally conductive, and has at least one reflection surface for reflecting the laser light ray from the laser element so as to change travelling direction of the laser light ray. The wavelength conversion layer converts wavelength of the laser light ray from the light guide member to result in a laser beam, and contacts the light guide member so that heat from the wavelength conversion layer is transferred to the substrate through the light guide member.

Abstract: A polishing system includes a platen to hold a polishing pad, a carrier head to hold a substrate against the polishing pad, a conditioner including a conditioner head to hold a conditioner disk against the polishing pad, a motor to move the conditioner head laterally movable relative to the platen, a conditioning disk cleaning station positioned adjacent the platen to clean the conditioning disk, and a controller configured to cause the motor to, during polishing of the substrate, move the conditioner head back and forth between a first position with the conditioner head over the polishing pad and a second position with the conditioner head in the conditioner disk cleaning station.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.