Patents by Inventor Hui Chi

Hui Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SHIELDING STRUCTURES
    Publication number: 20210091029
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Detecting the cleanness of wafer after post-CMP cleaning
    Patent number: 10957609
    Abstract: A method includes performing Chemical Mechanical Polish (CMP) on a wafer, placing the wafer on a chuck, performing a post-CMP cleaning on the wafer, and determining cleanness of the wafer when the wafer is located on the chuck.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ting Yen, Chi-Ming Tsai, Hui-Chi Huang
  • Chemical mechanical polishing apparatus and method
    Patent number: 10953514
    Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
  • CHEMICAL MECHANICAL POLISHING APPARATUS AND METHOD
    Publication number: 20210078130
    Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
  • Compositions for use in chemical mechanical polishing
    Patent number: 10947414
    Abstract: A polishing composition for a chemical mechanical polishing process includes abrasive particles, at least one chemical additive, and a non-aqueous solvent.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-I Chih, Chih-Chieh Chang, Hui-Chi Huang, Kei-Wei Chen
  • CHEMICAL MECHANICAL PLANARIZATION TOOL
    Publication number: 20210053184
    Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Tung-Kai Chen, Shang-Yu Wang, Wan-Chun Pan, Zink Wei, Hui-Chi Huang, Kei-Wei Chen
  • Novel CMP Pad Design and Method of Using the Same
    Publication number: 20210053179
    Abstract: An embodiment is a polishing pad including a top pad and a sub pad that is below and contacting the top pad. The top pad includes top grooves along a top surface and microchannels extending from the top grooves to a bottom surface of the top pad. The sub pad includes sub grooves along a top surface of the sub pad.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Pin-Chuan Su, Jeng-Chi Lin, Guan-Yi Lee, Hui-Chi Huang, Kei-Wei Chen
  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20210020633
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Hsiang-Ku SHEN, Chih Wei LU, Hui-Chi CHEN, Jeng-Ya David YEH
  • MEGA-SONIC VIBRATION ASSISTED CHEMICAL MECHANICAL PLANARIZATION
    Publication number: 20210016415
    Abstract: A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Chun-Hao Kung, Shang-Yu Wang, Ching-Hsiang Tsai, Hui-Chi Huang, Kei-Wei Chen
  • METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210013301
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • CHEMICAL MECHANICAL POLISHING METHOD
    Publication number: 20200411329
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20200411377
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a n-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 3, 2020
    Publication date: December 31, 2020
    Inventors: Hui-Chi CHEN, HSIANG-KU SHEN, JENG-YA YEH
  • DISPLAY DEVICE
    Publication number: 20200395516
    Abstract: A display device is provided, including a display panel; a light-emitting element disposed under the display panel; an optical functional film disposed between the display panel and the light-emitting element. The optical functional film is capable of transmitting at least part of the light emitted from the light-emitting element. A diffuser film is disposed between the display panel and the light-emitting element. The haze of the diffuser film is greater than 85%, and the thickness of the diffuser film ranges from 0.1 mm to 0.3 mm.
    Type: Application
    Filed: May 14, 2020
    Publication date: December 17, 2020
    Inventors: Chia-Lun CHEN, Shih-Chang HUANG, Ming-Hui CHU, Chih-Chang CHEN, Kai-Hsien HSIUNG, Hui-Chi WANG, Wun-Yuan SU
  • Shielding structures
    Patent number: 10861810
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Metal-Insulator-Metal Structure and Methods of Fabrication Thereof
    Publication number: 20200365683
    Abstract: The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Clamping mechanism
    Patent number: 10773294
    Abstract: A clamping mechanism is provided to clamp a die set on a carrier of a machine. The clamping mechanism utilizes a first pushing block to push a locating shaft of the die set to allow a top surface of the locating shaft to contact a mounting surface of the carrier and utilizes a second pushing block to push the locating shaft to allow a first contacting surface of the locating shaft to contact a reference surface of a cage base such that the die set will not clamp on the carrier of the machine with shift or skew errors.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 15, 2020
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Hsin-Wei Chu, Pin-Jyun Chen, Ching-Hua Hsieh, Hui-Chi Chang, Po-Fu Hsu, Chien-Fa Huang
  • Chemical mechanical polishing method
    Patent number: 10777423
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Semiconductor device and a method for fabricating the same
    Patent number: 10734283
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Chi Chen, Hsiang-Ku Shen, Jeng-Ya David Yeh
  • Metal-insulator-metal structure and methods of fabrication thereof
    Patent number: 10734474
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Vehicle wheel
    Patent number: D891343
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 28, 2020
    Assignee: Dicastal North America, Inc.
    Inventors: Chao Han, Hui Chi