Patents by Inventor Hui Chi

Hui Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11340748
    Abstract: A light source module having a light emitting surface is provided. The light source module includes at least one substrate, at least one circuit layer, and at least one light emitting element. The at least one circuit layer is disposed on at least one surface of the at least one substrate, and the at least one circuit layer includes at least one circuit. An orthogonal projection of the at least one circuit onto the light emitting surface forms a circuit region, and a coverage rate of the circuit region on the light emitting surface is less than 50%. The at least one light emitting element is disposed on the at least one surface of the at least one substrate and is connected to the at least one circuit layer. In addition, a touch device having the light source module is also provided.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 24, 2022
    Assignee: CHAMP VISION DISPLAY INC.
    Inventors: Hung-Ming Li, Hui-Chi Chang
  • Patent number: 11342408
    Abstract: The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11338614
    Abstract: A wheel and a rim with weight reduction sockets are provided. The rim is made of an aluminum alloy and includes an inner flange, a middle portion and an outer flange, the inner flange, middle portion and outer flange are all annular and are connected end to end to form a cylindrical rim, in which weight reduction sockets are provided on the outer surface of the middle portion of the rim; the weight reduction sockets are rectangular ones, and are arranged in lattices in turn; and 3-5 rows of weight reduction sockets are arranged annularly on the outer surface of the middle portion of the rim.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 24, 2022
    Assignee: CITIC DICASTAL CO., LTD.
    Inventors: Zuo Xu, Xu Wang, Hanqi Wu, Zhen Li, Kaiqing Wang, Yule Zhou, Chuan Cheng, Changhai Li, Tiefeng Hu, Hui Chi
  • Patent number: 11315574
    Abstract: A mobile device, a system and a method for task management based on voice intercom function are provided. A mobile device receives a voice message associated with at least one task. Semantic information of the voice message is analyzed to determine at least one message receiver of the voice message and generate a task message. Another mobile device corresponding to one of the at least one message receiver receives the task message. Task management information associated with the at least one task is updated according to the semantic information of the voice message.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 26, 2022
    Assignee: Wistron Corporation
    Inventors: Hui Chi Hsieh, Yu-Chen Yeh
  • Publication number: 20220102221
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Cheng Hong Yang, Shih-Hao Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11282993
    Abstract: A display device is provided, including a display panel; a light-emitting element disposed under the display panel; an optical functional film disposed between the display panel and the light-emitting element. The optical functional film is capable of transmitting at least part of the light emitted from the light-emitting element. A diffuser film is disposed between the display panel and the light-emitting element. The haze of the diffuser film is greater than 85%, and the thickness of the diffuser film ranges from 0.1 mm to 0.3 mm.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 22, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Lun Chen, Shih-Chang Huang, Ming-Hui Chu, Chih-Chang Chen, Kai-Hsien Hsiung, Hui-Chi Wang, Wun-Yuan Su
  • Patent number: 11264232
    Abstract: Methods for cleaning integrated circuit (IC) wafers after undergoing planarization processes (for example, chemical mechanical polishing processes) and associated cleaning units and/or planarization units are disclosed herein. An exemplary method includes configuring outlet areas of spray nozzles to deliver a cleaning solution to optimal locations of the IC wafer and delivering the cleaning solution via the spray nozzles having the configured outlet areas to the IC wafer. Each of the outlet areas is configured to achieve a particular velocity of the cleaning solution exiting the outlet area, such that the cleaning solution reaches a particular location of the IC wafer depending on the particular velocity. In some implementations, the cleaning solution enters inlet areas of the spray nozzles at the same flow rate and the cleaning solution exits the outlet areas of the spray nozzles at different velocities.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chien-Ping Lee, Hui-Chi Huang
  • Publication number: 20220050940
    Abstract: Embodiments of the present disclosure provide a method and a system for optimizing metal stamping process parameters, thereby performing die parameters optimization and stamping forming curve optimization to achieve various design goals. Embodiments of the present disclosure automatically model the die parameters and stamping forming curves, and import them into an optimization process. Embodiments of the present disclosure use a response surface method to fit a linear polynomial function, and then perform optimization on a response surface to obtain a best die parameters values combination and a best stamping forming curve.
    Type: Application
    Filed: September 29, 2020
    Publication date: February 17, 2022
    Inventors: Ching-Hua HSIEH, Hui-Chi CHANG, Po-Tse SU, Pin-Jyun CHEN, Fu-Chuan HSU
  • Patent number: 11239142
    Abstract: A package structure and method for forming the same are provided. The package structure includes a conductive layer formed over a first substrate, and a dielectric layer formed over the conductive layer. The package structure includes a metal-insulator-metal (MIM) capacitor embedded in the dielectric layer, and a shielding layer formed over the MIM capacitor. The shielding layer is insulated from the MIM capacitor by the dielectric layer. The package structure also includes a first through via formed through the MIM capacitor, and the first through via is connected to the conductive layer, and the first through via is insulated from the shielding layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Hui-Chi Chen, Tien-I Bao, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20220017780
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: January 20, 2022
    Inventors: JI CUI, CHI-JEN LIU, CHIH-CHIEH CHANG, KAO-FENG LIAO, PENG-CHUNG JANGJIAN, CHUN-WEI HSU, TING-HSUN CHANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUI-CHI HUANG
  • Patent number: 11222946
    Abstract: Methods of forming a 3-dimensional metal-insulator-metal super high density (3D-MIM-SHD) capacitor and semiconductor device are disclosed herein. A method includes depositing a base layer of a first dielectric material over a semiconductor substrate and etching a series of recesses in the base layer. Once the series of recesses have been etched into the base layer, a series of conductive layers and dielectric layers may be deposited within the series of recesses to form a three dimensional corrugated stack of conductive layers separated by the dielectric layers. A first contact plug may be formed through a middle conductive layer of the corrugated stack and a second contact plug may be formed through a top conductive layer and a bottom conductive layer of the corrugated stack. The contact plugs electrically couple the conductive layers to one or more active devices of the semiconductor substrate.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Mu Yin, Hung-Chao Kao, Dian-Hau Chen, Hui-Chi Chen, Hsiang-Ku Shen, Yen-Ming Chen
  • Patent number: 11217479
    Abstract: A multiple metallization scheme in conductive features of a device uses ion implantation in a first metal layer to make a portion of the first metal layer soluble to a wet cleaning agent. The soluble portion may then be removed by a wet cleaning process and a subsequent second metal layer deposited over the first metal layer. An additional layer may be formed by a second ion implantation in the second metal layer may be used to make a controllable portion of the second metal layer soluble to a wet cleaning agent. The soluble portion of the second metal layer may be removed by a wet cleaning process. The process of depositing metal layers, implanting ions, and removing soluble portions, may be repeated until a desired number of metal layers are provided.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Ying Ho, Fang-I Chih, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20210371702
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: December 2, 2021
    Inventors: JI CUI, CHI-JEN LIU, LIANG-GUANG CHEN, KEI-WEI CHEN, CHUN-WEI HSU, LI-CHIEH WU, PENG-CHUNG JANGJIAN, KAO-FENG LIAO, FU-MING HUANG, WEI-WEI LIANG, TANG-KUEI CHANG, HUI-CHI HUANG
  • Patent number: 11189538
    Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Mao-Nan Wang, Kuo-Chin Chang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20210366490
    Abstract: A mobile device, a system and a method for task management based on voice intercom function are provided. A mobile device receives a voice message associated with at least one task. Semantic information of the voice message is analyzed to determine at least one message receiver of the voice message and generate a task message. Another mobile device corresponding to one of the at least one message receiver receives the task message. Task management information associated with the at least one task is updated according to the semantic information of the voice message.
    Type: Application
    Filed: July 9, 2020
    Publication date: November 25, 2021
    Applicant: Wistron Corporation
    Inventors: Hui Chi Hsieh, Yu-Chen Yeh
  • Patent number: 11167587
    Abstract: A wheel and a rim with a weight reduction inner flange are provided. The rim includes an inner flange, a middle portion and an outer flange which are all annular and connected end to end to form an annular rim, in which the inner flange or the outer flange includes multiple groups of edge weight reduction sockets arranged side by side on one side of the inner cavity of a hub, and multiple groups of inner weight reduction sockets arranged side by side are provided inside the edge weight reduction sockets on the rim; a group of edge weight reduction sockets includes a first edge weight reduction socket and a second edge weight reduction socket at the edge of the inner flange or the outer flange, and the first edge weight reduction socket is in the shape of a right-angled triangle having round angles.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 9, 2021
    Assignee: CITIC Dicastal CO., LTD.
    Inventors: Zuo Xu, Zhen Li, Xu Wang, Kaiqing Wang, Yule Zhou, Chuan Cheng, Changhai Li, Tiefeng Hu, Hui Chi
  • Publication number: 20210323086
    Abstract: Systems and methods for static and dynamic calibration may be used to provide alignment of a measurement beam from a coherence imaging (CI) measurement system relative to a processing beam from a material processing system. In these systems and methods, a calibration measurement output may be obtained from the CI measurement system and/or from an auxiliary sensor. Future measurements performed by the CI measurement system may be modified based on, at least in part, the calibration measurement output.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 21, 2021
    Inventors: Jordan A. Kanko, Hui-Chi Chen, Moemen Y. Moemen, Paul J.L. Webster
  • Publication number: 20210328005
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a bottom electrode, a first oxide layer adjacent the bottom electrode, and a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is over the first high-k dielectric layer and a second oxide layer is adjacent the middle electrode. A second high-k dielectric layer may be over the middle electrode and the second oxide layer, a top electrode may be over the second high-k dielectric layer.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 21, 2021
    Inventors: Hsiang-Ku SHEN, Ming-Hong KAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20210327720
    Abstract: A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Yen-Ting Chen, Chun-Hao Kung, Tung-Kai Chen, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11145751
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ju Chen, Su-Hao Liu, Chun-Hao Kung, Liang-Yin Chen, Huicheng Chang, Kei-Wei Chen, Hui-Chi Huang, Kao-Feng Liao, Chih-Hung Chen, Jie-Huang Huang, Lun-Kuang Tan, Wei-Ming You