Patents by Inventor Hui Chi

Hui Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
    Publication number: 20200235225
    Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Yao-De CHIOU, Hui-Chi CHEN, Jeng-Ya YEH
  • CLAMPING MECHANISM
    Publication number: 20200188984
    Abstract: A clamping mechanism is provided to clamp a die set on a carrier of a machine. The clamping mechanism utilizes a first pushing block to push a locating shaft of the die set to allow a top surface of the locating shaft to contact a mounting surface of the carrier and utilizes a second pushing block to push the locating shaft to allow a first contacting surface of the locating shaft to contact a reference surface of a cage base such that the die set will not clamp on the carrier of the machine with shift or skew errors.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Hsin-Wei Chu, Pin-Jyun Chen, Ching-Hua Hsieh, Hui-Chi Chang, Po-Fu Hsu, Chien-Fa Huang
  • Semiconductor Device including a High Density MIM Capacitor and Method
    Publication number: 20200176557
    Abstract: Methods of forming a 3-dimensional metal-insulator-metal super high density (3D-MIM-SHD) capacitor and semiconductor device are disclosed herein. A method includes depositing a base layer of a first dielectric material over a semiconductor substrate and etching a series of recesses in the base layer. Once the series of recesses have been etched into the base layer, a series of conductive layers and dielectric layers may be deposited within the series of recesses to form a three dimensional corrugated stack of conductive layers separated by the dielectric layers. A first contact plug may be formed through a middle conductive layer of the corrugated stack and a second contact plug may be formed through a top conductive layer and a bottom conductive layer of the corrugated stack. The contact plugs electrically couple the conductive layers to one or more active devices of the semiconductor substrate.
    Type: Application
    Filed: May 1, 2019
    Publication date: June 4, 2020
    Inventors: Jin-Mu Yin, Hung-Chao Kao, Dian-Hau Chen, Hui-Chi Chen, Hsiang-Ku Shen, Yen-Ming Chen
  • Shielding Structures
    Publication number: 20200168574
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: April 23, 2019
    Publication date: May 28, 2020
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • METHODS TO CLEAN CHEMICAL MECHANICAL POLISHING SYSTEMS
    Publication number: 20200130138
    Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Chieh CHANG, Yen-Ting CHEN, Hui-Chi HUANG, Kei-Wei CHEN
  • Semiconductor Structure with Polyimide Packaging and Manufacturing Method
    Publication number: 20200105634
    Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.
    Type: Application
    Filed: May 14, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Fan Huang, Mao-Nan Wang, Kuo-Chin Chang, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • METAL-INSULATOR-METAL CAPACITIVE STRUCTURE AND METHODS OF FABRICATING THEREOF
    Publication number: 20200105863
    Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor structure includes forming a bottom electrode, forming a first oxide layer adjacent the bottom electrode, and depositing a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is then formed over the first high-k dielectric layer and a second oxide layer is formed adjacent the middle electrode. A second high-k dielectric layer may be deposited over the middle electrode and the second oxide layer and a top electrode over the second high-k dielectric layer.
    Type: Application
    Filed: June 12, 2019
    Publication date: April 2, 2020
    Inventors: Hsiang-Ku SHEN, Ming-Hong KAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • MULTIPLE METALLIZATION SCHEME
    Publication number: 20200043784
    Abstract: A multiple metallization scheme in conductive features of a device uses ion implantation in a first metal layer to make a portion of the first metal layer soluble to a wet cleaning agent. The soluble portion may then be removed by a wet cleaning process and a subsequent second metal layer deposited over the first metal layer. An additional layer may be formed by a second ion implantation in the second metal layer may be used to make a controllable portion of the second metal layer soluble to a wet cleaning agent. The soluble portion of the second metal layer may be removed by a wet cleaning process. The process of depositing metal layers, implanting ions, and removing soluble portions, may be repeated until a desired number of metal layers are provided.
    Type: Application
    Filed: January 11, 2019
    Publication date: February 6, 2020
    Inventors: Hsin-Ying Ho, Fang-I Chih, Hui-Chi Huang, Kei-Wei Chen
  • Chemical Mechanical Polish Slurry and Method of Manufacture
    Publication number: 20200043745
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Application
    Filed: November 2, 2018
    Publication date: February 6, 2020
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • COMPOSITIONS FOR USE IN CHEMICAL MECHANICAL POLISHING
    Publication number: 20200040221
    Abstract: A polishing composition for a chemical mechanical polishing process includes abrasive particles, at least one chemical additive, and a non-aqueous solvent.
    Type: Application
    Filed: July 3, 2019
    Publication date: February 6, 2020
    Inventors: Fang-I CHIH, Chih-Chieh CHANG, Hui-Chi HUANG, Kei-Wei CHEN
  • Magnetic Slurry for Highly Efficient CMP
    Publication number: 20200043747
    Abstract: A chemical-mechanical polishing (CMP) system includes a head, a polishing pad, and a magnetic system. The slurry used in the CMP process contains magnetizable abrasives. Application and control of a magnetic field, by the magnetic system, allows precise control over how the magnetizable abrasives in the slurry may be drawn toward the wafer or toward the polishing pad.
    Type: Application
    Filed: December 3, 2018
    Publication date: February 6, 2020
    Inventors: Yen-Ting Chen, Chun-Hao Kung, Tung-Kai Chen, Hui-Chi Huang, Kei-Wei Chen
  • SELF-HEALING POLISHING PAD
    Publication number: 20200039022
    Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.
    Type: Application
    Filed: July 16, 2019
    Publication date: February 6, 2020
    Inventors: Chun-Hao Kung, Hui-Chi Huang, Kei-Wei Chen, Yen-Ting Chen
  • Semiconductor Device Structure with Interconnect Structure and Method for Forming the Same
    Publication number: 20200043777
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Application
    Filed: April 12, 2019
    Publication date: February 6, 2020
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20200035780
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Metal-Insulator-Metal Structure and Methods of Fabrication Thereof
    Publication number: 20200035779
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Application
    Filed: October 10, 2018
    Publication date: January 30, 2020
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Semiconductor device and method for fabricating the same
    Patent number: 10529824
    Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-De Chiou, Hui-Chi Chen, Jeng-Ya Yeh
  • Multi-Layer Passivation Structure and Method
    Publication number: 20200006183
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: January 2, 2020
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Dian-Hau Chen, Yen-Ming Chen
  • METHODS TO ENHANCE NERVE REGENERATION UTILIZING NEURAL STEM CELLS AND IL12P40
    Publication number: 20190351022
    Abstract: The present application provides a composition and methods to enhance nerve regeneration utilizing at least one component of neural stem cells or IL12p40. The composition comprises neural stem cells and a neurotrophic factor, which is constructed by IL12p40 as at least one subunit. The methods to enhance nerve regeneration comprise providing a nerve regeneration composition comprising a neurotrophic factor containing IL12p40 as at least one subunit to a subject. The composition of the methods can further comprise neural stem cells.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 21, 2019
    Applicant: National Health Research Institutes
    Inventors: Ing-Ming CHIU, Ya-Hui CHI, Don-Ching LEE
  • Vehicle wheel
    Patent number: D885294
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 26, 2020
    Assignee: DICASTAL NORTH AMERICA, INC.
    Inventors: Hui Chi, Yingjie Wang, Chao Han
  • Vehicle wheel
    Patent number: D889356
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Dicastal North America, Inc.
    Inventors: Chao Han, Hui Chi