Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device is formed on a substrate and includes a first first-type metal-oxide-semiconductor field effect transistor (MOSFET) and a second first-type MOSFET. The first first-type MOSFET includes a first gate structure, a first source area and a first drain area on the substrate. The second first-type MOSFET includes a second gate structure, a second source area, and a second drain area on the substrate. A first pocket implant process is applied to the first first-type MOSFET via a first photomask, while a second pocket implant process is applied to the second first-type MOSFET via a second photomask. The first and second gate structures are facing different directions.

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component, a second package component, and a first set of conductive elements coupling the first package component to the second package component. A first polymer-comprising material is molded on the first package component and surrounds the first set of conductive elements. The first polymer-comprising material has an opening therein exposing a top surface of the second package component. A third package component and a second set of conductive elements couples the second package component to the third package component.

Abstract: A semiconductor package comprises a top package and a bottom package with fan-out interconnect structures. A plurality of inter-package connectors electrically connect the top package and the bottom package, and are located near a perimeter of the semiconductor package. A first material is located in a space delimited by a lower surface of the top package, an upper surface of the bottom package, and the inner-most inter-package connectors of the semiconductor package, wherein the first material partially fills the space. A second material different from the first material encapsulates the inter-package connectors.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.

Abstract: A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the die. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of the die.

Abstract: An apparatus for use in a charged particle multi-beam lithography system is disclosed. The apparatus includes a plurality of charged particle doublets each having a first aperture and each configured to demagnify a beamlet incident upon the first aperture thereby producing a demagnified beamlet. The apparatus further includes a plurality of charged particle lenses each associated with one of the charged particle doublets, each having a second aperture, and each configured to receive the demagnified beamlet from the associated charged particle doublet and to realize one of two states: a switched-on state, wherein the demagnified beamlet is allowed to travel along a desired path, and a switched-off state, wherein the demagnified beamlet is prevented from traveling along the desired path. In embodiments, the first aperture is greater than the second aperture, thereby improving particle beam efficiency in the charged particle multi-beam lithography system.

Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

Abstract: An apparatus includes a mold chase, which includes a top portion and an edge ring having a ring-shape. The edge ring is underlying and connected to an edge of the top portion. The edge ring has an injection port and a venting port. A molding guide kit is configured to be inserted into the injection port. The molding guide kit includes a front sidewall having a curved front edge.

Abstract: Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such.

Abstract: A display device includes a first substrate, a second substrate, a plurality of pixel units, a driving unit, a common electrode, and a column insulation structure. The pixel units are formed at a display area of the first substrate. The driving unit is formed at a non-display area of the first substrate. The common electrode is formed on an inner surface of the second substrate. The connecting layer is electronically connected between two conductive layers of the driving unit. The column insulation structure overlaps the connecting layer and is formed between the first and the second substrates.

Abstract: A display device is provided. The display device includes a switch including a gate, an active layer disposed on the gate, a source electrode connected to the active layer, and a drain electrode connected to the active layer. In particular, the distance between the edge of the gate electrode and the edge of the active layer is 1.2 to 3 ?m. The drain electrode includes a connection portion, an oblique portion, and an extension portion, wherein the oblique portion is disposed between the connection portion and the extension portion, and wherein at least a part of the oblique portion overlaps with the gate electrode.

Abstract: The present disclosure provides a display device, including: a display region, a driving element, and the display region electrically connected to the driving element through a plurality of signal line pairs. In particular, at least one of the signal line pairs includes a first conductive line and a second conductive line, and the first conductive line is electrically isolated from the second conductive line. In the signal line pair, at least a part of the first conductive line overlaps the second conductive line.

Abstract: The disclosure provides a display device including a first substrate, a display region disposed above the first substrate; a second substrate; a sealant disposed between the first substrate and the second substrate and outside the display region; and, a plurality of spacers disposed within the sealant. In particular, the first substrate and the second substrate are bonded together via the sealant. Further, the first substrate has a side wall including a first cutting crack surface and a first median crack surface, wherein a roughness of the first cutting crack surface is different from that of the first median crack surface.

Abstract: A display device includes a first substrate, a second substrate, a plurality of pixel units, a driving unit, and column insulation structure. The first substrate has a display area and a non-display area outside of the display area. The pixel units are formed at the display area of the first substrate and configured to receive an output signal. Formed at the non-display area of the first substrate, the driving unit includes first and second conductive layers, and first and second insulation layers which are alternately arranged. The connecting layer is connected between the first and second conductive layers via the through-holes formed at the first and second insulation layers. The column insulation structure corresponds to the connecting layer and is formed between the first and second substrates.

Abstract: Methods of packaging and dicing semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging and dicing semiconductor devices includes a first cutting process performed on a wafer to form a groove passing through a passivation layer and an interconnect structure on a scribe line region and a portion of a semiconductor substrate on the scribe line region. Next, a molding compound layer is formed on a frontside of the wafer to fill the groove. After performing a grinding process on a backside of the wafer to thin down the semiconductor substrate, a second cutting process is performed on the wafer to separate the individual dies. The second cutting process cuts through the molding compound layer in the groove and the semiconductor substrate underlying the groove.

Abstract: A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.

Abstract: A touch integrated panel includes a first substrate having a first outer surface and a first inner surface where a thin film transistor array is formed, a second substrate having a second outer surface and a second inner surface, and a liquid crystal layer sandwiched between the first inner surface and the second inner surface, wherein a touch sense pattern for sensing touch operations performed on the panel and a key sense pattern for sensing whether a function key is touched are formed on the first outer surface or the second outer surface.