Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: A method of forming a semiconductor structure includes forming a fin over a substrate, forming a bottom source/drain over the substrate surrounding a first portion of sidewalls of the fin, and forming a bottom spacer over the bottom source/drain and surrounding a second portion of the sidewalls of the fin. The method also includes forming a T-shaped gate stack over the bottom spacer and surrounding a third portion of the sidewalls of the fin, forming a top spacer over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the fin, and forming a top source/drain over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the fin. The T-shaped gate stack includes a gate dielectric, a gate conductor, and a gate metal extending outward from a portion of sidewalls of the gate conductor between the bottom and top spacers.

Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Abstract: An IC device includes capacitor elements formed within the same wiring level and in an area of the wiring level that is between a pair of wiring lines. This area may be an area that is not previously utilized, may be an area where dummy metal features were traditionally utilized, or the like. In a first implementation, the capacitor elements include a first capacitor comb interleaved with a second capacitor comb. In another implementation, the capacitor element is a perforated capacitor plate. The geometry of the interleaved capacitor combs and the open area of the perforations may be tuned in order to achieve or meet a predetermined uniform wiring level metal density requirement(s). The IC device may utilize a capacitor formed at least in part with the capacitor elements as a decoupling capacitor, a noise filter, a sensor, or the like.

Abstract: A nanosheet semiconductor structure and method for forming the same, where the nanosheet semiconductor structure includes a substrate and a nanosheet stack comprising vertically oriented nanosheets. A gate structure contacts and wraps around the vertically oriented nanosheets. A source layer and a drain layer are each disposed adjacent to the nanosheet stack. An inner spacer is disposed in contact with a bottom surface of the nanosheet stack. The method includes forming an alternating pattern of first spacers and second spacers on a semiconductor stack. The first spacers and one or more underlying portions of the semiconductor stack are removed thereby forming a plurality of trenches each adjacent to one or more of the second spacers. The plurality of trenches defines a plurality of vertically oriented nanosheets. A plurality of sacrificial spacers are formed each in contact with one or more vertically oriented nanosheets of the plurality of vertically oriented nanosheets.

Abstract: A nanosheet semiconductor structure and method for forming the same, where the nanosheet semiconductor structure includes a substrate and a nanosheet stack comprising vertically oriented nanosheets. A gate structure contacts and wraps around the vertically oriented nanosheets. A source layer and a drain layer are each disposed adjacent to the nanosheet stack. An inner spacer is disposed in contact with a bottom surface of the nanosheet stack. The method includes forming an alternating pattern of first spacers and second spacers on a semiconductor stack. The first spacers and one or more underlying portions of the semiconductor stack are removed thereby forming a plurality of trenches each adjacent to one or more of the second spacers. The plurality of trenches defines a plurality of vertically oriented nanosheets. A plurality of sacrificial spacers are formed each in contact with one or more vertically oriented nanosheets of the plurality of vertically oriented nanosheets.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

Abstract: A method of forming a semiconductor structure includes forming a fin over a substrate, forming a bottom source/drain over the substrate surrounding a first portion of sidewalls of the fin, and forming a bottom spacer over the bottom source/drain and surrounding a second portion of the sidewalls of the fin. The method also includes forming a T-shaped gate stack over the bottom spacer and surrounding a third portion of the sidewalls of the fin, forming a top spacer over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the fin, and forming a top source/drain over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the fin. The T-shaped gate stack includes a gate dielectric, a gate conductor, and a gate metal extending outward from a portion of sidewalls of the gate conductor between the bottom and top spacers.

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.