Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.

Abstract: A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.

Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Abstract: Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

Abstract: According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack disposed over a first portion of a substrate and a fin channel material disposed over a second portion of the substrate, patterning the nanosheet stack disposed over the first portion of the substrate to form two or more nanosheet channels for at least one nanosheet field-effect transistor, patterning the fin channel material disposed over the second portion of the substrate to form one or more fins for at least one fin field-effect transistor, forming a first dielectric layer surrounding the nanosheet channels and the one or more fins, patterning a mask layer over the one or more fins, removing the first dielectric layer surrounding the nanosheet channels, removing the mask layer, forming a second dielectric layer surrounding the nanosheet channels and over the first dielectric layer surrounding the one or more fins, and forming a gate conductive layer over the second dielectric layer.

Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.

Abstract: Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

Abstract: A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.

Abstract: A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.

Abstract: A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

Abstract: A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

Abstract: A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.