Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a blanket target layer. There is then formed over the blanket target layer a patterned mask layer. There is then measured, while employing an optical method, a linewidth of the patterned mask layer to determine a patterned mask layer measured linewidth. There is then determined a deviation of the patterned mask layer measured linewidth from a patterned mask layer target linewidth. There is then etched, while employing a plasma etch method, the blanket target layer to form a patterned target layer while employing the patterned mask layer as a etch mask layer.

Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.

Abstract: A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least nitrogen and oxygen.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blanket second masking layer to assist in providing the floating gate electrode with a sharply pointed tip within at least either an upper edge of the floating gate electrode or sidewall of the floating gate electrode. The sharply pointed tip provides the split gate field effect transistor (FET) device with enhanced data erasure performance.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least hydrogen and carbon monoxide.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.

Abstract: Hard mask trimming with a thin hard mask layer and a top protection layer is disclosed. During fabrication of a semiconductor device, the device has a primary layer, a lower layer, and an upper layer. The primary layer, which may be a polysilicon layer, has a critical dimension specification. The lower layer is over the polysilicon layer, and is subsequently hard mask trimmed to satisfy the critical dimension specification of the primary layer. The upper layer is over the lower layer, and has a high-etching selectivity as compared to the lower layer. The upper layer substantially prevents thickness loss of the lower layer during hard mask trimming. Each of the upper layer and the lower layer may be Si3N4, SiON, or SiO2. Additionally, the upper layer may be polysilicon.

Abstract: Partial photoresist etching is disclosed. A film on a semiconductor wafer includes a hard mask, doped polysilicon below the hard mask, undoped polysilicon below the doped polysilicon, and a stop layer below the undoped polysilicon. Photoresist etching is performed through the hard mask and the doped polysilicon by using a photoresist mask. After the photoresist mask is removed, photoresist-free etching is performed through the undoped polysilicon through to the stop layer by using the hard mask. A semiconductor device is disclosed that may be fabricated using this partial photoresist etching process.

Abstract: A new process is provided for the creation of an improved gate spacer profile. A layer of hardmask material is patterned over the surface of a layer of gate material. The layer of gate material is etch in accordance with the patterned layer of hardmask material, reducing the thickness of the patterned layer of hardmask material. A liner oxide is formed, a film of gate spacer material is deposited over the liner material. The layer of spacer material is etched, forming gate spacers and at the same time the remaining layer of hardmask material.

Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

Abstract: A method for forming a trench having upper rounded corners comprising the following steps. A substrate having an oxide layer formed thereover is provided. A hard mask layer is formed over the oxide layer. A patterned patterning layer is formed over the hard mask layer leaving one or more portions of the hard mask layer exposed. The hard mask layer is patterned using the patterned patterning layer as a mask to form a patterned hard mask layer having one or more openings exposing one or more portions of the oxide layer. The patterned patterning layer is removed. The oxide layer is patterned using the patterned hard mask layer as a mask using a first trench etching process to etch through the oxide layer at the one or more exposed portions of the oxide layer and into the substrate to form one or more shallow trenches within the substrate having upper rounded corners at the respective interfaces between substrate and patterned oxide layer.

Abstract: A process for forming a contact hole opening, featuring the use in situ dry etching, and photoresist removal procedures, used to define the desired contact hole opening; in an overlying hard mask layer, in the dielectric layer, and in an underlying insulator stop layer, has been developed. The process features the initial definition of the contact hole opening, in an overlying hard mask insulator layer, accomplished in a chamber of a dry etch tool, followed by removal of an overlying, contact hole defining photoresist shape, performed in situ, in the same dry etch chamber. The contact hole opening is then transferred to the dielectric layer via a selective dry etch procedure, performed in situ, in the dry etch chamber, using the overlying hard mask insulator layer as an etch mask.

Abstract: A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said silicon nitride layer. Suitable materials for the buffer layer that have been found to be effective include silicon oxide and silicon oxynitride with the latter offering some additional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: A method of patterning a gate electrode layer having an underlying high-k dielectric layer comprising the following sequential steps. A substrate is provided. A high-k dielectric layer is formed over the substrate. A gate electrode layer is formed over the high-k dielectric layer. The gate electrode layer is patterned to form a patterned gate electrode layer, the patterned gate electrode layer having exposed side walls and a top. Sidewall spacers are formed over the exposed side walls of the patterned gate electrode layer, the sidewall spacers having tops. The patterned gate electrode layer is etched to pull the top of the patterned gate electrode layer down from the tops of the sidewall spacers. The exposed portions of the high-k dielectric layer not under the sidewall spacers and the pulled-down patterned gate electrode layer are removed.

Abstract: The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted. Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said sidon nitride layer. Suitable materials for the buffer layer that have been found to be infective include silicon oxide and silicon oxynitride with the latter offering some ditional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: A method for forming a patterned oxygen containing plasma etchable layer. There is first provided a substrate. There is then formed upon the substrate a blanket oxygen containing plasma etchable layer. There is then formed upon the blanket oxygen containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer the blanket hard mask layer to form a patterned hard mask layer. There is then etched while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer the blanket oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etchable layer.

Abstract: A method of forming a borderless contact, comprising the following steps. A substrate having an exposed conductive structure is provided. An oxynitride etch stop layer is formed over the substrate and the exposed conductive structure. An oxide dielectric layer is formed over the oxynitride etch stop layer. The oxide dielectric layer is etched with an etch process having a high selectivity of oxide-to-oxynitride to form a contact hole therein exposing a portion of the oxynitride etch stop layer over at least a portion of the exposed conductive structure. The etch process not appreciably etching the oxynitride etch stop layer and including: a fluorine containing gas; an inert gas; and a weak oxidant. The exposed portion of the oxynitride etch stop layer over at least a portion of the conductive structure is removed. A borderless contact is formed within the contact hole. The borderless contact being in electrical connection with at least a portion of the conductive structure.