Abstract: A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O.sub.

Abstract: A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

Abstract: A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nitride layer formed on a semiconductor wafer. A polysilicon layer is subsequently formed on the silicon nitride layer. A shallow trench is then created by photolithography and dry etching processes. The photoresist is subsequently removed in which an oxide layer is form in the shallow trench and on polysilicon layer for the purpose of isolation. A selective etching is used to etch the oxide layer. A CMP is performed to produce a planarized surface on a silicon wafer.

Abstract: A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer.

Abstract: A new method for planarizing a shallow trench isolation is disclosed by using a polysilicon layer or bottom anti-reflective coating (BARC) to form a reverse tone with a taper profile. The formation of the shallow trench isolation described includes a pad layer, and a silicon nitride layer formed-on a semiconductor wafer. Trenches are created by photolithography and dry etching processes. An oxide layer is formed in the trenches for the purpose of isolation. A polysilicon layer or bottom anti-reflective coating is subsequently formed on the oxide layer. A plurality of openings are generated in the polysilicon or the BARC layer. An etching is used to etch the oxide layer, thereby forming a reverse tone having a taper profile. A Chemical Mechanical Polishing is performed to planarize the surface of a semiconductor wafer.

Abstract: A process for forming a planarized, insulator, or silicon oxide filled shallow trench has been developed. The process features a hybrid planarization procedure, comprised of an initial dry etching cycle, used to remove all but about 100 to 500 Angstroms of silicon oxide, from subsequent device regions, or regions outside the insulator filled trench. Silicon oxide residing on the insulator filled trench is protected by a photoresist shape. A final chemical mechanical polishing procedure is than employed to remove both the silicon oxide, on the insulator filled shallow trench, as well as removing the remaining silicon oxide on silicon nitride, in subsequent device regions. An endpoint monitoring procedure allows the detection of the remaining 100 to 500 Angstroms of silicon oxide, on silicon nitride.

Abstract: A method for forming a via through a nitrogenated silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a nitrogenated silicon oxide layer. There is then formed upon the nitrogenated silicon oxide layer a patterned photoresist layer. Finally, there is then etched the nitrogenated silicon oxide layer through a reactive ion etch (RIE) plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer to form a via through the nitrogenated silicon oxide layer. The reactive ion etch (RIE) method employs an etchant gas composition comprising: (1) a perfluorocarbon having a carbon:fluorine atomic ratio at least about 1:3; (2) oxygen; and (3) argon.

Abstract: The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process.

Abstract: A method for creating a tapered profile insulator shape, on an underlying silicon nitride layer, using a photoresist shape as a mask, has been developed. A two step dry etching procedure is used, featuring a first dry etching phase, using an etching chemistry comprised of argon, CHF.sub.3 and CF.sub.4, resulting in a tapered profile insulator shape, underlying the photoresist shape. A second dry etching phase, exhibiting high etch rate selectivity between insulator layer and underlying silicon nitride, via use of an etching chemistry comprised of argon, CHF.sub.3, CH.sub.2 F.sub.2, and CH.sub.3 F, is used to remove residual insulator layer from the underlying silicon nitride layer, without significant attack of the underlying silicon nitride layer.

Abstract: A method for monitoring and controlling a plasma etch method for forming a patterned layer. There is first provided a substrate having a blanket layer formed thereover, the blanket layer having a patterned photoresist layer formed thereupon. There is then etched through a plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer the blanket layer to form a patterned layer. The plasma etch method is monitored through an optical emission spectroscopy (OES) method which monitors a minimum of a first plasma etchant component which relates to a chemical etching of the blanket layer and a second plasma etchant component which relates to a physical sputter etching of the blanket layer and the patterned photoresist layer.

Abstract: A method of improving electrostatic chucking efficiency between a silicon wafer which has an oxide layer formed on a back side and a susceptor positioned in a wafer processing chamber wherein the back side is opposite to the side of the wafer to be processed for integrated circuit devices including the steps of first forming an electrically conducting layer on top of the oxide layer by transforming to a more hydrophilic oxide structure and then positioning the wafer on the susceptor with the electrically conducting layer contacting the susceptor.

Abstract: The etch rate in a plasma etching system has been monitored in-situ by using optical emission spectroscopy to measure the intensities of two or more peaks in the radiation spectrum and then using the ratio of two such peaks as a direct measure of etch rate. Examples of such peaks occur at 338.5 and 443.7 nm and at 440.6 and 437.6 nm for the fluoride/SOG system. Alternately, the intensities of at least four such peaks may be measured and the product of two ratios may be used. Examples of peaks used in this manner occurred at 440.5, 497.2 and 502.3 nm, also for the fluoride/SOG system. The method is believed to be general and not limited to fluoride/SOG.

Abstract: A dye containing solution composition for use in forming optical recording media comprises about 0.1 to about 5 parts cyanine dye; about 0.1 to about 5 parts polyvinyl acetate resin and about 100 to about 90 parts co-solvents. The dye containing solution is applied to a substrate of an optical recording medium by a spin coating process to form a recording layer having a uniform thickness. The resultant optical recording medium is suitable for reading and writing with a laser beam.