Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.

Abstract: A cooling device for a vehicle battery may include a cooling fin receiving heat generated by a plurality of battery cells and discharging the heat to an outside, and a bendable heat-transfer body receiving heat from the cooling fin, the bendable heat-transfer body being composed of a bimetal so that the bimetal is spaced from a vehicle body panel when the temperature decreases and such that the bimetal is bent to be brought into contact with the vehicle body panel when the temperature increases.

Abstract: A head mounted display device is provided. The head mounted display device includes a left eye display unit which displays an image for a left eye and is disposed along a trajectory of a left eye ellipse having a first eccentricity, and a left eye lens which faces the left eye display unit and refracts the image for the left eye in a direction of a user's left eye.

Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.

Abstract: A method for detecting biomaterial by means of a dye having a linear upconversion fluorescent property is provided. The method includes the steps of: i) preparing a fluorophore having a linear upconversion fluorescent property; ii) reacting the fluorophore and biomaterial to obtain a reaction complex thereof; iii) exciting the reaction complex by means of a light source having a longer wavelength than the maximum light-emitting wavelength of the fluorophore; and iv) detecting and measuring the light-emitting signal having a shorter wavelength than the wavelength of the excited light emitted from the excited reaction complex. A system and a kit for detecting biomaterial using a dye having a linear upconversion fluorescent property are also provided.

Abstract: Tandem solar cells comprising two or more solar cells connected in a solar cell stack via pn diode tunnel junctions and methods for fabricating the tandem solar cells using epitaxial lift off and transfer printing are provided. The tandem solar cells have improved tunnel junction structures comprising a current tunneling layer integrated between the p and n layers of the pn diode tunnel junction that connects the solar cells.

Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.