Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes at least two active strip regions, a hybrid fin structure, and a gate stack. The hybrid fin structure is disposed between the at least two active strip regions. The gate stack is across the at least two active strip regions and the hybrid fin structure. A portion of the hybrid fin structure exposed by the gate stack is free of a high dielectric constant material.

Abstract: Provided is a conductive structure and a method for forming such a structure. The method includes forming a treatable layer by depositing a layer comprising a metal over a structure; performing a directional treatment process on a targeted portion of the treatable layer to convert the targeted portion to a material different from a non-targeted portion of the treatable layer, wherein the directional treatment process is selected from the group consisting of nitridation, oxidation, chlorination, carbonization; and selectively removing the non-targeted portion from the structure, wherein the targeted portion remains over the structure.

Abstract: A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

Abstract: An electronic device includes a cover plate assembly, a frameless display panel assembly, and an adhesive layer. The cover plate assembly has a first major surface. A peripheral region of the first major surface has a first area. The frameless display panel assembly is disposed below the cover plate assembly and has a second major surface. A peripheral region of the second major surface has a second area smaller than the first area. The adhesive layer is disposed between the peripheral region of the first major surface and the peripheral region of the second major surface. The adhesive layer is a frame-shaped and elastic colloid. The adhesive layer, the cover plate assembly, and the frameless display panel assembly together form a closed space after being pressed together, and the closed space has a spacing smaller than 200 microns.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.

Abstract: A method includes: providing a modulation circuit and a driving circuit, the modulation circuit configured to generate a temperature-dependent voltage and provide the same to the driving circuit; determined an operation mode of a memory array; providing a first current corresponding to a positive temperature coefficient by the driving circuit in response to the operation mode being a read operation on the memory array; and providing a second current corresponding to a negative temperature coefficient by the driving circuit in response to the operation mode being a write operation on the memory array.

Abstract: A method includes: providing a modulation circuit including a first resistive element, a second resistive element and a third resistive element; providing a memory array and a regulator connecting the modulation circuit to the memory array, wherein the regulator includes a transistor; determining an operation mode of the memory array; generating a first voltage at a drain terminal of the transistor, wherein the first voltage corresponds to a positive, negative zero temperature coefficient according to a first resistance ratio and a second resistance ratio; during a read operation, providing a first driving current to the memory array in response to the first voltage corresponding to the positive temperature coefficient; and during a write operation, providing a second driving current to the memory array in response to the first voltage corresponding to the negative temperature coefficient.

Abstract: A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.

Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

Abstract: A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the conductive layers and the dielectric layers, a charge storage layer disposed between the conductive layers and the channel layer, an insulating layer penetrating through the conductive layers and the dielectric layers and disposed between the charge storage layer and the multi-layer stack, and a first conductive pillar and a second conductive pillar enclosed by the channel layer.

Abstract: The present disclosure provides improved processes for the preparation of Relugolix and intermediates thereof. Relugolix is prepared via intermediates (M7) and (M8): wherein X is as described herein. Present disclosure also provides three additional routes to prepare Relugolix and intermediates thereof, where the starting material of ethyl 2-amino-4-methyl-5-(4-nitrophenyl)thiophene-3-carboxylate (SM1) is protected by coupling with an acyl chloride, a hydroxylamine or an oxime.

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.

Abstract: An operation method of a detachable camera, wherein the detachable camera includes a camera body, a camera holder, a driving element and a control circuit, the driving element is controlled by the driving element to control the camera holder, and the operation method, performed by the control circuit, includes: triggered by a trigger signal to determine whether the camera body is on the camera holder, setting a driving current of the driving element as a first current if the camera body is on the camera holder, and setting the driving current of the driving element as a second current if the camera body is not on the camera holder, wherein the second current is lower than the first current.

Abstract: A data center heat recovery system includes a building heat pump system providing a first liquid when an ambient temperature is lower than a first preset temperature, a heat exchanger receiving the first liquid from the building heat pump system when the ambient temperature is lower than the first preset temperature, and modular data centers. Each of the modular data centers includes an air chiller and a data center. Each of the modular data centers is coupled to the heat exchanger through a second pipeline containing a second fluid. When the ambient temperature is higher than a second preset temperature, the air chiller cools the second fluid. When the ambient temperature is lower than the first preset temperature, the heat exchanger collects heat from the second fluid, and the heat exchanger transports the collected heat to the building heat pump system through the first fluid in the first pipeline.

Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and a memory material layer. The multi-layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a first direction. The memory material layer is disposed between the channel layer and each of the conductive layers and the dielectric layers. The conductive pillars extend in the first direction, wherein the at least three conductive pillars are aligned along a second direction substantially perpendicular to the first direction.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: Systems and methods are disclosed for generating cluster quantum states usable for quantum computing. An example system can generate a plurality of qumodes. The plurality of qumodes can include at least two successive qumodes in frequency domain, wherein a frequency spacing between two successive qumodes is equal to a free-spectral range of an optical frequency comb. The plurality of qumodes can include a plurality of bipartite entangled states. A cluster quantum state can be generated by modulating a phase of a portion of the optical fields associated with the plurality of qumodes received from the optical frequency comb, at one or more modulation frequencies. In some embodiments, each of the one or more modulation frequencies can be equal to an integral multiple of the free-spectral-range. In certain embodiments, a property of a cluster graph (such as a dimension of the cluster graph) associated with the cluster quantum state can be controlled by adjusting one or more modulation frequencies.

Abstract: A containerized data system, including a container body, a first cabinet array, a second cabinet array and a plurality of first air-conditioning devices. The first cabinet array and the second cabinet array are positioned in the container body and spaced apart from each other. Air intake areas of the first cabinet array and the second cabinet array communicates with a cold aisle connection space of the container body. Heat dissipation areas of the first cabinet array and the second cabinet array communicate with a hot aisle connection space of the container body. Air inlets of the first air-conditioning devices are communicated with the hot aisle connection space to collect the hot air flow in the container body, and air outlets of the plurality of first air-conditioning devices are communicated with the cold aisle connection space to convey the cold air flow to the container body.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.