Abstract: A memory device includes transistor structures and memory arc wall structures. The memory arc wall structures are embedded in the transistor structures. The transistor structure includes a dielectric column, a source electrode and a drain electrode, a gate electrode layer and a channel wall structure. The source electrode and the drain electrode are located on opposite sides of the dielectric column. The gate electrode layer is around the dielectric column, the source electrode, and the drain electrode. The channel wall structure is extended from the source electrode to the drain electrode and surrounds the dielectric column. The channel wall structure is disposed between the gate electrode layer and the source electrode, between the gate electrode layer, and the drain electrode, and between the gate electrode layer and the dielectric column. The memory arc wall structure is extended on and throughout the channel wall structure.

Abstract: A trench isolation structure and method of making the same is provided. The trench isolation structure comprises a trench in a substrate, the trench having a bottom surface and sidewalls. A polycrystalline material is at least partially in the trench and an amorphous layer is over the polycrystalline material.

Abstract: The present invention provides an RFID yarn module comprising a polymer substrate having a first surface and a second surface opposite to the first surface, a metal layer, and a first adhesive layer formed on the metal layer, and a first polymer material layer formed on the first the adhesive layer, a second adhesive layer, and a first protection layer. The metal layer is formed on the first surface of the polymer substrate and has an RFID element electrically connected to the metal layer. The second adhesive layer is formed on the first polymer material layer and is corresponding to the RFID element. The first protection layer is formed on the second adhesive layer. Alternatively, the present invention provides a method for making the RFID yarn module in which a roll-to-roll process for mass manufacturing is utilized to make the RFID yarn module.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: A light-emitting diode includes a substrate, a distributed Bragg reflector (DBR) structure and a semiconductor layered structure. The DBR structure is disposed on the substrate. The semiconductor layered structure is disposed on the DBR structure opposite to the substrate, and is configured to emit a light having a first wavelength. The DBR structure has a reflectance of not greater than 30% for the light having the first wavelength, and a reflectance of not smaller than 50% for a laser beam having a second wavelength that is different from the first wavelength.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.

Abstract: In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Abstract: A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a sidewall spacer. The channel layer is over a substrate. The gate structure wraps around the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The sidewall spacer is on a sidewall of the first source/drain epitaxial structure and includes a first dielectric layer and a second dielectric layer over the first dielectric layer and in contact with first source/drain epitaxial structure. The first dielectric layer and the second dielectric layer include different materials.

Abstract: An electrostatic discharge (ESD) protection device including the following components is provided. A first transistor includes a first gate, a first N-type source region, and an N-type drain region. A second transistor includes a second gate, a second N-type source region, and the N-type drain region. The N-type drain region is located between the first gate and the second gate. An N-type drift region is located in a P-type substrate between the first gate and the second gate and is located directly below a portion of the first gate and directly below a portion of the second gate. The N-type drain region is located in the N-type drift region. A P-type barrier region is located in the P-type substrate below the N-type drift region. The P-type barrier region has an overlapping portion overlapping the N-type drift region. There is at least one first opening in the overlapping portion.

Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.

Abstract: A metal oxide semiconductor (MOS) with multiple drain vias includes a semiconductor substrate, which is divided into a gate region, a source region and a drain region. On the same surface of the semiconductor substrate in the gate region, a connection layer is formed in the source region and the drain region with a low-resistance metal material. A plurality of conductive elements, such as solder balls, can be directly arranged on the connection layer, so that the MOS can be soldered to the circuit board through the conductive elements distributed on the same surface. In the drain region, there are a plurality of vias. The inside of each via is filled with the connection layer and extends to the inside of the semiconductor substrate. With the aforementioned structure, the MOS has the advantage of low on-resistance RDS(ON).

Abstract: A temperature control device includes a temperature sensor configured to detect a temperature within a server. When the temperature in the server is below a preset temperature, the control unit controls an interior heating assembly to heat the server, and closes a ventilation assembly to retain heat within the server. When the temperature in the server has reached the preset temperature, the control unit controls the heating assembly to stop the internal heating, and controls the ventilation assembly to open, to allow dissipation of the heat from the server.

Abstract: An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: A wafer inspection method and inspection apparatus are provided. On a wafer having layout lines connecting electrode points of individual dies in series, the dies within a matrix range are inspected one after another in turn in a column/row control means by a first switch group and a second switch group of a probe card, so that each die is selectively configured in a test loop of a test process by turning on/off of a corresponding switch. Thus, after inspection of a die under inspection (a selected die) within the matrix range is complete, the column/row control means is used to switch to a next die to achieve fast switching. Accordingly, for the inspection procedure of each die within the matrix region, a conventional procedure of moving one after another in turn can be eliminated, significantly reducing the total test time needed and enhancing inspection efficiency.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.