Abstract: A coated metal alloy substrate with at least one chamfered edge, a process for producing a coating a metal alloy substrate, and an electronic device having a housing comprising a coated metal alloy substrate are described. The coated metal alloy substrate with at least one chamfered edge comprises a hydrophobic anti-fingerprint layer deposited on the metal alloy substrate, a passivation layer deposited on the at least one chamfered edge, and a water based paint layer deposited on the passivation layer.

Abstract: A piezoelectric valve driver device is provided. A first driver is connected to a first side of a valve. A second driver is connected to a second side of the valve. A power charging circuit is coupled between an external power source and a second voltage. A charging and discharging current controller is connected to the first driver, the second driver and the power charging circuit, and is configured to control currents of the first driver, the second driver and the power charging circuit. When a driver circuit switches the valve from a closed state to an open state, the first driver provides a first voltage to the first side of the valve, and the second voltage that is outputted to the second side of the valve by the second driver is discharged to output a discharging current to the external power source through the power charging circuit.

Abstract: An image processing method for a video processor, for generating an extrapolated frame according to a previous frame and a current frame, includes steps of: projecting a plurality of motion vectors (MVs) to the extrapolated frame subsequent to the current frame; determining whether a block of the extrapolated frame is projected by at least two of the MVs; selecting at least two candidate MVs from the MVs projected to the block when the block is projected by at least two of the MVs; calculating a blended MV which is a mixture of the at least two candidate MVs, and projecting the blended MV to the previous frame; obtaining a reference MV corresponding to position of the previous frame projected by the blended MV; and comparing the reference MV with the at least two candidate MVs, to select a final MV for the block from the at least two candidate MVs.

Abstract: Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A di(2-ethylhexyl) terephthalate composition is provided. The di(2-ethylhexyl) terephthalate composition comprises di(2-ethylhexyl)terephthalate, at least one of a first component, a second component and a third component, and a fourth component When the di(2-ethylhexyl) terephthalate composition is characterized by gas chromatography (GC), the first component is eluted at a retention time ranging from 4.8 minutes to 6.0 minutes, the second component is eluted at a retention time ranging from 9.0 minutes to 10.0 minutes, the third component is eluted at a retention time ranging from 10.1 minutes to 12.0 minutes, and the fourth component is eluted at a retention time ranging from 21.0 minutes to 22.1 minutes. The ratio of the total area of the chromatographic peaks indicating the first component, second component, and third component to the area of the chromatographic peaks indicating the fourth component is 0.135 to 1.720.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: The disclosure features a system that includes a plurality of material tanks, each of which includes at least one material for forming a chemical composition and includes a first recirculation loop; at least one mixing tank in which the materials from the material tanks are mixed to form a chemical composition, the mixing tank including a second recirculation loop; and at least one holding tank configured to continuously receive the chemical composition from the mixing tank, the holding tank including a third recirculation loop. The system may further include a plurality of fluid flow controller units and be configured to form material and chemical composition flows in an in-process steady state.

Abstract: A display may have an array of pixels such as liquid crystal display pixels. The display may include short pixel rows that span only partially across the display and full-width pixel rows that span the width of the display. The gate lines coupled to the short pixel rows may extend into the inactive area of the display. Supplemental gate line loading structures may be located in the inactive area of the display to increase loading on the gate lines that are coupled to short pixel rows. The supplemental gate line loading structures may include data lines and doped polysilicon that overlap the gate lines in the inactive area. In displays that combine display and touch functionality into a thin-film transistor layer, supplemental loading structures may be used in the inactive area to increase loading on common voltage lines that are coupled to short rows of common voltage pads.

Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.

Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.

Abstract: A lens assembly includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens, wherein the first, second, third, fourth, fifth, and sixth lenses are arranged in order from an object side to an image side along an optical axis. The first lens is a meniscus lens with positive refractive power and includes a convex surface facing the object side and a concave surface facing the image side. The second, third, and fourth lenses are with refractive power. The fifth lens is with positive refractive power and includes a convex surface facing the image side. The sixth lens is with negative refractive power and includes a concave surface facing the image side. The lens assembly satisfies: 3<D1/T6<9; wherein D1 is an effective optical diameter of the convex surface of the first lens and T6 is a thickness of the sixth lens.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.