Patents by Inventor Hung Chao

Hung Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11214872
    Abstract: A cyclical epitaxial deposition system and a gas distribution module are provided. The gas distribution module includes an inflow element having a plurality of inlet holes, a guide assembly, and an outflow element. The guide assembly disposed between the inflow and outflow elements includes a plurality of guide channels separate from one another and a plurality of temporary gas retention trenches respectively corresponding to the guide channels. Each of the guide channels is in fluid communication with the corresponding inlet hole. The outflow element has a plurality of diffusion regions respectively corresponding to the gas retention trenches, and a plurality of outlet channels respectively corresponding to the diffusion regions. Each of the diffusion regions has a plurality of diffusion apertures, and each of the temporary gas retention trenches is in fluid communication with the corresponding outlet channel through the diffusion apertures in the corresponding diffusion region.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 4, 2022
    Assignee: GOLD CARBON CO., LTD.
    Inventors: Chien-Te Hsieh, Yeou-Fu Lin, Chia-Hung Chao
  • Patent number: 11126247
    Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 21, 2021
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Ching-Hung Chao, Hou-Yuan Lin, Mou-Ming Ma, Chun-Kun Lan, Po-Chang Tseng, Hung-Yen Chen, Chun-Yu Wang, Yih-Neng Lin
  • Publication number: 20210201742
    Abstract: An electronic device is provided. The electronic device includes: a display panel and a host. The host is electrically connected to the display panel, and includes a processing unit and a graphics processing unit. The processing unit executes a driver program of the graphics processing unit and a specific program to render a display image of the specific program, wherein the display image includes a user interface. The processing unit obtains position information about a static area of the user interface. In response to the processing unit obtaining the position information about the static area of the user interface, the graphics processing unit performs a burn-in-prevention process on the static area via the driver program to generate an output image, and transmits the output image to the display panel for displaying.
    Type: Application
    Filed: September 29, 2020
    Publication date: July 1, 2021
    Applicant: GIGA-BYTE TECHNOLOGY CO.,LTD.
    Inventors: Hou-Yuan LIN, Ching-Hung CHAO, Po-Chang TSENG, Hung-Yen CHEN
  • Publication number: 20210098564
    Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 1, 2021
    Inventors: Jin-Mu YIN, Hung-Chao KAO, Hsiang-Ku SHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20200385885
    Abstract: A cyclical epitaxial deposition system is provided. The cyclical epitaxial deposition system includes a deposition chamber, a conveyance device, and a gas distribution module. The conveyance device is used to continuously convey a substrate to pass through the deposition chamber along a conveyance path. The gas distribution module is disposed in the deposition chamber and located above the conveyance path. The gas distribution module includes a plurality of precursor gas nozzles and purge gas nozzles that are not in communication with one another so as to guide at least one precursor gas and at least one purge gas to different regions of the substrate at the same time.
    Type: Application
    Filed: April 30, 2020
    Publication date: December 10, 2020
    Inventors: CHIEN-TE HSIEH, Yeou-Fu Lin, CHIA-HUNG CHAO
  • Publication number: 20200385869
    Abstract: A cyclical epitaxial deposition system and a gas distribution module are provided. The gas distribution module includes an inflow element having a plurality of inlet holes, a guide assembly, and an outflow element. The guide assembly disposed between the inflow and outflow elements includes a plurality of guide channels separate from one another and a plurality of temporary gas retention trenches respectively corresponding to the guide channels. Each of the guide channels is in fluid communication with the corresponding inlet hole. The outflow element has a plurality of diffusion regions respectively corresponding to the gas retention trenches, and a plurality of outlet channels respectively corresponding to the diffusion regions. Each of the diffusion regions has a plurality of diffusion apertures, and each of the temporary gas retention trenches is in fluid communication with the corresponding outlet channel through the diffusion apertures in the corresponding diffusion region.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 10, 2020
    Inventors: CHIEN-TE HSIEH, Yeou-Fu Lin, CHIA-HUNG CHAO
  • Publication number: 20200365683
    Abstract: The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10833222
    Abstract: A light-emitting diode, comprising a substrate that has a first surface and an opposing second surface. A reflection layer is disposed on the first surface of the substrate and a light-emitting diode structure is arranged on the second surface of the substrate. The light-emitting diode structure includes a first semiconducting layer, an active layer and a second semiconducting layer disposed consecutively on the second surface. A plurality of protruding asymmetric micro-structured elements define at least a part of the second surface of the substrate such that at least a portion of a surface of each micro-structured element is disposed at an obtuse angle to the first surface of the substrate when measured from within the respective micro-structured element. The first semiconducting layer and the second semiconducting layer respectively have a first electrode and a second electrode.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: November 10, 2020
    Assignee: The Penn State Research Foundation
    Inventors: Shizhuo Yin, Chang-Jiang Chen, Ju-Hung Chao, Wenbin Zhu
  • Patent number: 10755972
    Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao
  • Patent number: 10734474
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20200209939
    Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.
    Type: Application
    Filed: September 4, 2019
    Publication date: July 2, 2020
    Inventors: Ching-Hung Chao, Hou-Yuan Lin, Mou-Ming Ma, Chun-Kun Lan, Po-Chang Tseng, Hung-Yen Chen, Chun-Yu Wang, Yih-Neng Lin
  • Publication number: 20200176557
    Abstract: Methods of forming a 3-dimensional metal-insulator-metal super high density (3D-MIM-SHD) capacitor and semiconductor device are disclosed herein. A method includes depositing a base layer of a first dielectric material over a semiconductor substrate and etching a series of recesses in the base layer. Once the series of recesses have been etched into the base layer, a series of conductive layers and dielectric layers may be deposited within the series of recesses to form a three dimensional corrugated stack of conductive layers separated by the dielectric layers. A first contact plug may be formed through a middle conductive layer of the corrugated stack and a second contact plug may be formed through a top conductive layer and a bottom conductive layer of the corrugated stack. The contact plugs electrically couple the conductive layers to one or more active devices of the semiconductor substrate.
    Type: Application
    Filed: May 1, 2019
    Publication date: June 4, 2020
    Inventors: Jin-Mu Yin, Hung-Chao Kao, Dian-Hau Chen, Hui-Chi Chen, Hsiang-Ku Shen, Yen-Ming Chen
  • Publication number: 20200035779
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Application
    Filed: October 10, 2018
    Publication date: January 30, 2020
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20190355126
    Abstract: An image feature extraction method for a 360° image includes the following steps: projecting the 360° image onto a cube model to generate an image stack including a plurality of images having a link relationship; using the image stack as an input of a neural network, wherein when operation layers of the neural network performs padding operation on one of the plurality of images, the link relationship between the plurality of adjacent images is used such that the padded portion at the image boundary is filled with the data of neighboring images in order to retain the characteristics of the boundary portion of the image; and by the arithmetic operation of the neural network of such layers with the padded feature map, an image feature map is generated.
    Type: Application
    Filed: August 9, 2018
    Publication date: November 21, 2019
    Inventors: Min SUN, Hsien-Tzu CHENG, Chun-Hung CHAO, Tyng-Luh LIU
  • Publication number: 20190237622
    Abstract: A light-emitting diode, comprising a substrate that has a first surface and an opposing second surface. A reflection layer is disposed on the first surface of the substrate and a light-emitting diode structure is arranged on the second surface of the substrate. The light-emitting diode structure includes a first semiconducting layer, an active layer and a second semiconducting layer disposed consecutively on the second surface. A plurality of protruding asymmetric micro-structured elements define at least a part of the second surface of the substrate such that at least a portion of a surface of each micro-structured element is disposed at an obtuse angle to the first surface of the substrate when measured from within the respective micro-structured element. The first semiconducting layer and the second semiconducting layer respectively have a first electrode and a second electrode.
    Type: Application
    Filed: August 10, 2017
    Publication date: August 1, 2019
    Inventors: Shizhuo Yin, Chang-Jiang Chen, Ju-Hung Chao, Wenbin Zhu
  • Patent number: 10354913
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Patent number: 10264858
    Abstract: A waterproof zipper is provided with two halves, each including a half tape member and a row of protruding teeth along an inner edge of the half tape member; and a waterproof layer is secured to an inner surface of the halves. A process of manufacturing the waterproof zipper is also provided, including the steps of: (a) guiding the waterproof layer to a position above the two halves on a continuous flow production line, each half having a half tape member and a row of protruding teeth along an inner edge of the half tape member; (b) coating a waterproof layer on a releasing layer; (c) drying both the waterproof layer and the releasing layer in an oven.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: April 23, 2019
    Assignee: Win-Chain Knitting Co., Ltd.
    Inventor: Hung-Chao Chen
  • Patent number: 10150212
    Abstract: A hand tool includes a handle having a room defined therein. A first and second lugs extend from the front end of the handle. A space is defined between the first and second lugs and communicates with the room. A working part is to be connected with a bit, and has a pivotal portion which is pivotably connected between the two lugs. A plate is connected to at least one of the first and second lugs, and has multiple first recesses and a second recesses. A positioning member is located between the pivotal portion and the plate so as to be engaged with one of the first and second recesses to position an angular position of working part. The working part is able to be pivoted and received in the room in the handle.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 11, 2018
    Assignees: Easy Tool Enterprise Co., Ltd.
    Inventor: Hung-Chao Yu
  • Publication number: 20180350664
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Application
    Filed: November 1, 2017
    Publication date: December 6, 2018
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Publication number: 20180151421
    Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.
    Type: Application
    Filed: March 20, 2017
    Publication date: May 31, 2018
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao