Patents by Inventor Hung Chih Chen

Hung Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252554
    Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Pin-Shiang Chen, Hung-Chih Chang, Chee Wee Liu, Samuel C. Pan
  • Publication number: 20190244934
    Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Publication number: 20190237423
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, an encapsulant, a first RDL structure, and a conductive terminal. The encapsulant is aside the first die, encapsulating sidewalls of the first die. The first RDL structure is on the first die and the encapsulant. The conductive terminal is electrically connected to first die through the RDL structure. The first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20190227601
    Abstract: A lifting device is applied to an input assembly, and includes: a base, a supporting base, and a connecting rod mechanism, where the base bears the input assembly and includes a lower protruding portion; the supporting base is movably disposed corresponding to the base and includes a base portion and a notch, and the notch is disposed corresponding to the lower protruding portion; the connecting rod mechanism includes an output rod and an input rod, where the output rod is connected to the supporting base; the input rod is linked with the output rod, and drives the output rod to move, so that the supporting base moves relative to the base, and when movement of the supporting base makes the lower protruding portion move from the notch to the base portion, the base ascends by a height.
    Type: Application
    Filed: November 21, 2018
    Publication date: July 25, 2019
    Inventors: Yen-Chih KUO, Hung-Cheng LEE, Tzu-Ming YANG, Cheng-Shi JIANG, Chao-Kai HUANG, Jeng-Hong CHIU, Chih-Ming CHEN, Chih-Liang CHIANG
  • Patent number: 10360342
    Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Chih Ou, Chun-Yao Ku, Wen-Hao Chen
  • Patent number: 10354978
    Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 16, 2019
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Publication number: 20190214366
    Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Publication number: 20190214367
    Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu, Li-Chih Fang
  • Patent number: 10335692
    Abstract: An apparatus for recording game history is coupled between a game host and a game console and performs a game history recording and interaction method. The apparatus communicates with the game host through a first wireless unit, and communicates with the game console through a second wireless unit, to receive game operation information generated from operations of the game console. The apparatus receives a video signal outputted by the game host through a video input port. The processing module is coupled to the wireless units and the video input port respectively and is used to obtain the game operation information from the wireless units and generate operation information images corresponding to the game operation information. The processing module superimposes the operation information images on the video signal correspondingly to form game history video data and outputs the superimposed game history video data to a display device for display.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: July 2, 2019
    Assignee: Aten International Co., Ltd.
    Inventors: Kuo-feng Kao, Hung-Chi Chu, Hui-Ju Lin, Chia-Chih Chen
  • Publication number: 20190200484
    Abstract: An electronic device includes a body and a shape memory element. The body includes an opening at a bottom surface of the electronic device. The shape memory element is twistably disposed in the opening, extended along an axis, and includes a first end which is fixed on the body, and a second end relative to the first end. When the temperature of the shape memory element is below a predetermined temperature range, the shape memory element is in a first shape and the second end is positioned inside the opening. When the temperature of the shape memory element is greater than the predetermined temperature range, the shape memory element is twisted to deform into a second shape, and the second end protrudes out of the opening.
    Type: Application
    Filed: June 27, 2018
    Publication date: June 27, 2019
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Hsueh-Chih Peng, Shun-Bin Chen, Huei-Ting Chuang, Pao-Min Huang
  • Patent number: 10332856
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 10331250
    Abstract: A touch panel is provided. The touch panel includes a substrate having a touch area and a peripheral area adjacent to the touch area. A transparent conductive layer is disposed on the substrate, the transparent conductive layer includes a touch-sensing portion and a wiring portion, wherein the touch-sensing portion is electrically connected to the wiring portion, and wherein the touch-sensing portion is disposed corresponding to the touch area and the wiring portion is disposed corresponding to the peripheral area. A metal layer is disposed on the wiring portion of the transparent conductive layer and corresponding to the peripheral area. An insulating layer is disposed on the metal layer and corresponding to the peripheral area. A touch display device including the touch panel is also provided.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 25, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Chih Chen, Tung-Chang Tsai, Hung-Sheng Cho
  • Patent number: 10326088
    Abstract: An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate. The oxide layer is located on the hydrophobic layer and has plural segments. The hydrophilic layer is located on the segments of the oxide layer, and the oxide layer is located between the hydrophilic layer and the hydrophobic layer. The semiconductor layer is located on the hydrophilic layer, and the hydrophilic layer is located between the semiconductor layer and the oxide layer. The source/drain layer connects across the semiconductor layer on the segments of the oxide layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 18, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Chih Chen, Hung-Chuan Liu, Zong-Xuan Li, Wei-Tsung Chen
  • Publication number: 20190181135
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Shang-Chuan PAI, Wei-Chung WU, Szu-Chi CHEN, Sheng-Chih CHUANG, Yin-Ting LIN, Pei-Chun YU, Han-Pei LIU, Jung-Tsun CHUANG, Chieh-Yao CHUANG, Hung-Wei CHEN
  • Patent number: 10321054
    Abstract: A panoramic image stitching method includes acquiring a plurality of first images, converting camera image plane coordinates of each first image of the plurality of first images into virtual image plane coordinates for generating a second image according a world coordinate system, identifying a plurality of feature points on the second image, calibrating coordinates of the plurality of feature points on the second image, generating a calibrated second image according to calibrated coordinates of the plurality of feature points on the second image, and stitching a plurality of calibrated second images for generating a panoramic image.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 11, 2019
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Hsuan-Ying Chen, Hung-Chih Chiang, Shui-Chin Yeh, Ming-Liang Chen
  • Publication number: 20190165180
    Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.
    Type: Application
    Filed: February 23, 2018
    Publication date: May 30, 2019
    Inventors: Hung-Lin CHEN, Shiuan-Jeng Lin, Wen-Chih Chiang, Po-Ming Chen, Tza-Hao Wang
  • Publication number: 20190165167
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chou LIN, Yi-Cheng CHIU, Karthick MURUKESAN, Yi-Min CHEN, Shiuan-Jeng LIN, Wen-Chih CHIANG, Chen-Chien CHANG, Chih-Yuan CHAN, Kuo-Ming WU, Chun-Lin TSAI
  • Patent number: 10297661
    Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Cheng Chiu, Wen-Chih Chiang, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Karthick Murukesan
  • Publication number: 20190148361
    Abstract: A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.
    Type: Application
    Filed: April 28, 2018
    Publication date: May 16, 2019
    Inventors: Hung-Chih LU, Chien-Mao Chen
  • Publication number: 20190145480
    Abstract: An adjustable damper includes a base, a first and second slidable members, a movable seat, a mass unit, and a first and second cantilevers. The first slidable member is slidably disposed on the base in a first direction. The movable seat is slidably disposed on the base in a second direction orthogonal to the first direction. The second slidable member is slidably disposed on the movable seat in the second direction. The mass unit is slidably disposed on the movable seat in the first direction. The first cantilever is fixed to a first connecting member. The first connecting member is connected to the movable seat. The first slidable member movably is disposed on the first cantilever. The second cantilever is fixed to a second connecting member. The second connecting member is connected to the mass unit. The second slidable member is movably disposed on the second cantilever.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 16, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hung-I LU, Chien-Chih LIAO, Jen-Ji WANG, Yun-Chiao CHEN