Patents by Inventor Hung-Chih Hsieh
Hung-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250147430Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.Type: ApplicationFiled: December 26, 2024Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chih HSIEH, Ming-Hsiao WENG
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Patent number: 12216412Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.Type: GrantFiled: November 22, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Hsieh, Ming-Hsiao Weng
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Publication number: 20240085804Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chih HSIEH, Ming-Hsiao WENG
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Publication number: 20240069449Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chih HSIEH, Yen-Liang CHEN
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Patent number: 11852981Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.Type: GrantFiled: December 23, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Hsieh, Ming-Hsiao Weng
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Patent number: 11841622Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.Type: GrantFiled: March 14, 2022Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Hsieh, Yen-Liang Chen
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Publication number: 20230359135Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark , each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
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Patent number: 11726413Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.Type: GrantFiled: April 4, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
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Patent number: 11656391Abstract: A method for performing DBO measurements utilizing apertures having a single pole includes using a first aperture plate to measure X-axis diffraction of a composite grating. In some embodiments, the first aperture plate has a first pair of radiation-transmitting regions disposed along a first diametrical axis and on opposite sides of an optical axis that is aligned with a center of the first aperture plate. Thereafter, in some embodiments, a second aperture plate, which is complementary to the first aperture plate, is used to measure Y-axis diffraction of the composite grating. By way of example, the second aperture plate has a second pair of radiation-transmitting regions disposed along a second diametrical axis and on opposite sides of the optical axis. In some cases, the second diametrical axis is substantially perpendicular to the first diametrical axis.Type: GrantFiled: May 22, 2020Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chih Hsieh, Kai Wu, Yen-Liang Chen, Kai-Hsiung Chen, Po-Chung Cheng, Chih-Ming Ke
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Publication number: 20220221804Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.Type: ApplicationFiled: April 4, 2022Publication date: July 14, 2022Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
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Publication number: 20220197153Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Inventors: Hung-Chih HSIEH, Yen-Liang CHEN
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Patent number: 11294293Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.Type: GrantFiled: March 7, 2019Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chih Hsieh, Kai-Hsiung Chen, Po-Chung Cheng
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Patent number: 11288019Abstract: A memory management method for a storage device having a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of physical blocks. The method includes: scanning the plurality of physical blocks to identify one or more bad physical blocks; performing a bad physical block remapping operation on the one or more bad physical blocks to update a virtual block stripe management table; and performing a writing operation under a multiple plane write mode based on the virtual block stripe management table.Type: GrantFiled: August 9, 2018Date of Patent: March 29, 2022Assignee: Shenzhen EpoStar Electronics Limited CO.Inventors: Hung-Chih Hsieh, Hsiu-Hsien Chu, Yu-Hua Hsiao
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Patent number: 11275314Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.Type: GrantFiled: April 26, 2021Date of Patent: March 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chih Hsieh, Yen-Liang Chen
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Publication number: 20210271175Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.Type: ApplicationFiled: April 26, 2021Publication date: September 2, 2021Inventors: Hung-Chih HSIEH, Yen-Liang CHEN
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Publication number: 20210271174Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.Type: ApplicationFiled: December 23, 2020Publication date: September 2, 2021Inventors: Hung-Chih HSIEH, Ming-Hsiao WENG
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Patent number: 10990023Abstract: A method of overlay error measurement includes disposing a reference pattern module over a substrate. The substrate includes first and second overlay measurement patterns in first and second locations. The reference pattern module includes first and second reference patterns. The method includes creating a first overlap of the first reference pattern with the first overlay measurement pattern and a second overlap of the second reference pattern with the second overlay measurement pattern. The method further includes determining a first overlay error between the first reference pattern of the reference pattern module and the first overlay measurement pattern of the substrate and determining a second overlay error between the second reference pattern and the second overlay measurement pattern. The method also includes determining a total overlay error between the first and second overlay measurement patterns of the substrate based on the first and second overlay errors.Type: GrantFiled: February 27, 2020Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chih Hsieh, Yen-Liang Chen
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Publication number: 20210116819Abstract: An overlay metrology tool and diffraction-based overlay measurements are described herein. The tool includes a light source for generating an incident light that illuminates stacked overlay targets formed within material layers of a wafer and a light sensing system for measuring characteristics of a diffracted light beam reflected from the surface of the wafer. During a single illumination of the wafer and without rotating a polarization of the incident light beam, the light sensing system generates three components of the diffracted light beam having one or more polarizations and intensities, according to an overlay recipe associated with the stacked overlay targets.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Hung-Chih Hsieh, Chun-Liang Lung
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Patent number: 10983005Abstract: A spectroscopic overlay metrology system and corresponding spectroscopic overlay metrology methods are disclosed herein for improving overly measurement accuracy, optimizing overlay recipes, and/or minimizing (or eliminating) asymmetry-induced overly error from overlay measurements. An exemplary method includes generating a diffraction spectrum by an overlay target from incident radiation having more than one wavelength. The diffraction spectrum includes a plurality of positive ordered diffracted beams and a plurality of negative ordered diffracted beams that are separated by wavelength, such that the diffraction spectrum includes more than one wavelength of a positive order and a negative order.Type: GrantFiled: June 15, 2017Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai Wu, Hung-Chih Hsieh, Kai-Hsiung Chen, Chih-Ming Ke, Yen-Liang Chen
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Patent number: 10969697Abstract: An overlay metrology tool and diffraction-based overlay measurements are described herein. The tool includes a light source for generating an incident light that illuminates stacked overlay targets formed within material layers of a wafer and a light sensing system for measuring characteristics of a diffracted light beam reflected from the surface of the wafer. During a single illumination of the wafer and without rotating a polarization of the incident light beam, the light sensing system generates three components of the diffracted light beam having one or more polarizations and intensities, according to an overlay recipe associated with the stacked overlay targets.Type: GrantFiled: October 18, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chih Hsieh, Chun-Liang Lung