Patents by Inventor Hung Cho Wang

Hung Cho Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11551736
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Hung-Cho Wang, Sheng-Chang Chen
  • Patent number: 11502126
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Wen Fu, Jun-Yao Chen, Sheng-Huang Huang, Hung-Cho Wang
  • Publication number: 20220359815
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20220352457
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate, in which the substrate has a cell region and a logic region adjacent to the cell region. A bottom electrode, a memory layer, and a top electrode are formed in sequence over the cell region of the substrate. A first spacer is formed extending upwards from the bottom electrode. A second spacer is formed extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay CHUANG, Hung-Cho WANG, Sheng-Chang CHEN, Jun-Yao CHEN, Chang-Jen HSIEH
  • Patent number: 11489107
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11469372
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A top electrode via couples the top electrode to an upper interconnect wire. A first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via. The first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane. The second angle is less than the first angle.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11469269
    Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Publication number: 20220319920
    Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
  • Patent number: 11437433
    Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chang Chen, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Huang Huang
  • Publication number: 20220263013
    Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Jun-Yao CHEN, Chun-Heng LIAO, Hung Cho WANG
  • Publication number: 20220246838
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Publication number: 20220246843
    Abstract: Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Harry-Hak-Lay Chuang, Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20220216268
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a first memory cell and a second memory cell over a substrate. A first dielectric layer is formed over and around the first and second memory cells. The first dielectric layer comprises sidewalls defining an opening spaced laterally between the first and second memory cells. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is disposed in the opening. A planarization process is performed on the first and second dielectric layers. At least a portion of the second dielectric layer is in the opening after the planarization process.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Patent number: 11380580
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
  • Patent number: 11355696
    Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yao Chen, Chun-Heng Liao, Hung Cho Wang
  • Publication number: 20220157886
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay CHUANG, Sheng-Wen FU, Jun-Yao CHEN, Sheng-Huang HUANG, Hung-Cho WANG
  • Patent number: 11322543
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang
  • Patent number: 11316096
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Publication number: 20220123051
    Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Inventors: Harry-Hak-Lay CHUANG, Wen-Chun YOU, Hung Cho WANG, Yen-Yu SHIH
  • Publication number: 20220093684
    Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 24, 2022
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang