Abstract: A planar winding transformer includes a magnetic core set and a multilayer circuit board. The magnetic core set includes two magnetic cores and two magnetic columns. The two magnetic cores are parallel to each other. The multilayer circuit board is disposed between two magnetic cores, and two magnetic columns penetrate through the multilayer circuit board. The multilayer circuit board includes two low voltage winding layers and one high voltage winding layer. Two low voltage winding layers are connected to each other in parallel, and the high voltage winding layer is disposed between two low voltage winding layers. When the high voltage winding layer receives a polarity current, at least one of the low voltage winding layers generates a corresponding induced current. Two magnetic cores and two magnetic columns form a closed path for magnetic flux.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: A capacitive ultrasonic transducer device includes a substrate, a first capacitive structure, a second capacitive structure, a first film structure and a second film structure. The first capacitive structure is disposed on the substrate, and includes a first electrode and a second electrode. A first gap and a dielectric layer are located between the first electrode and the second electrode. The second capacitive structure is disposed on the substrate, and includes a third electrode and a fourth electrode. A second gap is located between the third electrode and the fourth electrode. The first film structure is configured to seal the first gap. The second film structure is connected to the third electrode and the fourth electrode, and configured to seal the second gap. A first width between the first electrode and the second electrode is different from a second width of the second gap.

Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.

Abstract: Methods, systems, and devices for wireless communications are described. A network entity may transmit a set of spatially multiplexed synchronization signals in a same symbol period. The set of spatially multiplexed synchronization signals may indicate a parameter, such as a cell identifier, for the network entity. The network entity may select a sequence for each synchronization signal of the set. A user equipment (UE) may monitor for the set of spatially multiplexed synchronization signals during the same symbol period. The UE may differentiate each synchronization signal based on a respective sequence used to transmit each synchronization signal. The UE may determine that the set of spatially multiplexed synchronization signals were transmitted by the network entity using multiple antenna ports. The UE may determine the parameter for the network entity based on receiving the set of spatially multiplexed synchronization signals.

Abstract: An electrically conductive structure of lithium battery mainly comprises a housing, a lithium-battery-core, a cover plate, a first-metal-plate and a second-metal-plate.

Abstract: A package structure, including: a first packaging member having oppositely arranged first surface and second surface; a control chip covered by the first packaging member; a plurality of conductors provided on and protruding from the control chip and electrically connected to electrical contacts of the control chip, the conductors being covered by the first packaging member, and ends of the conductors facing away from the control chip being flush with the first surface; a wire pattern layer disposed on the first surface and electrically connected to the conductors; a light emitting element located on the first surface and electrically connected to the control chip via the wire pattern layer; and a second packaging member covering the light emitting element and affixed to the first surface and the wire pattern layer, a light beam emitted by the light emitting element being allowed to travel outward through the second packaging member.

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: An image processing method for a video processor, for generating an extrapolated frame according to a previous frame and a current frame, includes steps of: projecting a plurality of motion vectors (MVs) to the extrapolated frame subsequent to the current frame; determining whether a block of the extrapolated frame is projected by at least two of the MVs; selecting at least two candidate MVs from the MVs projected to the block when the block is projected by at least two of the MVs; calculating a blended MV which is a mixture of the at least two candidate MVs, and projecting the blended MV to the previous frame; obtaining a reference MV corresponding to position of the previous frame projected by the blended MV; and comparing the reference MV with the at least two candidate MVs, to select a final MV for the block from the at least two candidate MVs.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a device area and a peripheral area surrounding the device area; a via, disposed at the peripheral area and extending at least partially through the substrate; an insulating structure, disposed at the peripheral area, extending at least partially through the substrate and surrounding the via; and a doped region, disposed at the peripheral area, over or in the substrate and adjacent to the via.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: In some examples, a device can include an antenna to emit waves in a radiation pattern having a first beamwidth, a directional radiation control device located in a path of the waves, where the directional radiation control device is to receive the waves from the antenna and is shaped to cause the waves to be directed in a different radiation pattern having a second beamwidth that is larger than the first beamwidth.