Patents by Inventor Hung Huang

Hung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIVE-SIDE MOLD PROTECTION FOR SEMICONDUCTOR PACKAGES
    Publication number: 20230326821
    Abstract: Five-side mold protection for semiconductor packages is described. In an illustrative, non-limiting embodiment, a semiconductor package may include: a substrate comprising a top surface, a bottom surface, and four sidewalls; an electrical component comprising a backside and a frontside, where the frontside of the electrical component is coupled to the top surface of the substrate; and a molding compound, where the molding compound encapsulates the backside of the electrical component and the four sidewalls of the substrate.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: NXP B.V.
    Inventors: Kuan-Hsiang Mao, Wen Yuan Chuang, Wen Hung Huang
  • DECISION FEEDBACK EQUALIZATION EMBEDDED IN SLICER
    Publication number: 20230327921
    Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 12, 2023
    Inventors: Shu-Chun YANG, Wen-Hung Huang
  • SYSTEMS AND METHODS FOR INSERTING A FASTENER INTO A WAFER CARRIER
    Publication number: 20230302589
    Abstract: The present disclosure relates to systems and methods for affixing and/or removing a fastener from a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The screwdriver unscrews the fastener from the pod, and the fastener head is received within the lower sleeve.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 28, 2023
    Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • SELF-MODULATING POWER LASER CONTROL SYSTEM AND METHOD
    Publication number: 20230299552
    Abstract: The invention provides a self-modulating input electrical power laser control system and method. After the laser is turned on for a period of time, the control module reduces the initial electrical power to the operating power of the laser, and it maintains the operating power until the laser is turned off, which can reduce the extra power consumption and achieve the energy-efficiency.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Inventors: Kai-Hsiu LIAO, Su-Hung HUANG, Yi-Jing YOU
  • Charging module for electric vehicle
    Patent number: 11758699
    Abstract: A charging module for electric vehicle includes a power conversion unit, a heat dissipation unit, and a thermoelectric module. The power conversion unit includes a power conversion module disposed inside a cabinet, and the power conversion unit provides output power. The heat dissipation unit cools the power conversion unit through liquid cooling or air cooling. The thermoelectric module generates electrical energy based on a temperature difference between the power conversion unit and the heat dissipation unit during operation. The electrical energy is supplied to the power conversion unit and/or the heat dissipation unit.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 12, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Jui-Yuan Hsu, Ming-Hsien Hsieh, Kai-Hung Huang
  • Methods for removing a fastener from a wafer carrier
    Patent number: 11752582
    Abstract: The present disclosure relates to systems and methods for affixing and/or removing a fastener from a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The screwdriver unscrews the fastener from the pod, and the fastener head is received within the lower sleeve.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • High electron mobility transistor and method for fabricating the same
    Patent number: 11749740
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 5, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Bo-Rong Chen, Che-Hung Huang, Chun-Ming Chang, Yi-Shan Hsu, Chih-Tung Yeh, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Nanowire stack GAA device with selectable numbers of channel strips
    Patent number: 11742388
    Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: August 29, 2023
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
  • METHOD AND APPARATUS FOR SECURING SEMICONDUCTOR DEVICE CARRYING BOAT IN MULTI-BOAT TRAY
    Publication number: 20230268210
    Abstract: A tray of an automated handling system for transporting semiconductor devices includes: a receiving region that is configured to receive a boat, the boat carrying one or more semiconductor devices thereon; and a clamping mechanism that selectively clamps the boat, residing in the receiving region, to the tray. Suitably, the clamping mechanism is automatically disengaged when the tray is positioned in a designated location and automatically engaged when the tray is not positioned in the designated location, such that, when engaged, the clamping mechanism holds the boat, residing in the boat receiving region, securely within the tray, and when disengaged, the clamping mechanism releases the boat residing in the boat receiving region.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Inventors: CHUN-YU LIN, Chih-Hung Huang, Yu-Chen Chen, Cheng-Lung Wu, Jiun-Rong Pai
  • Bus system
    Patent number: 11734218
    Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, an SPI bus, a memory device electrically connected to the master device via the SPI bus, and a plurality of slave devices electrically connected to the master device via the eSPI bus. Each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line. After obtaining program code from the memory device via the master device, a first slave device is configured to decrypt the program code according to a first security code, and transmit the program code decrypted by the first security code to the slave devices via the control line, so that the program code decrypted by the first security code is decrypted in the slave devices according to a decryption sequence.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: August 22, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Huang, Kang-Fu Chiu, Hao-Yang Chang
  • High electron mobility transistor and method for fabricating the same
    Patent number: 11735644
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: August 22, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou, Chih-Tung Yeh
  • SEMICONDUCTOR PACKAGES
    Publication number: 20230260977
    Abstract: Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.
    Type: Application
    Filed: October 7, 2022
    Publication date: August 17, 2023
    Applicant: MediaTek Inc.
    Inventors: Hsiao-Yun CHEN, Chi-Hung HUANG, Yao-Tsung HUANG, Cheng-Jyi CHANG, Sheng Chieh CHANG
  • METHODS FOR REMOVING A FASTENER FROM A WAFER CARRIER
    Publication number: 20230256549
    Abstract: The present disclosure relates to systems and methods for affixing and/or removing a fastener from a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The screwdriver unscrews the fastener form the pod, and the fastener head is received within the lower sleeve.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • Wiring structure and method for manufacturing the same
    Patent number: 11728260
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 15, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Multiple Threshold Voltage Implementation Through Lanthanum Incorporation
    Publication number: 20230253256
    Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Inventors: Wen-Hung Huang, Kuo-Feng Yu, Jian-Hao Chen, Shan-Mei Liao, Jer-Fu Wang, Yung-Hsiang Chan
  • Integrated semiconductor die vessel processing workstations
    Patent number: 11721572
    Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Guan-Wei Huang, Chih-Hung Huang, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai
  • Conductive structure and wiring structure including the same
    Patent number: 11721634
    Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Semiconductor device package including stress buffering layer
    Patent number: 11721678
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
  • ACOUSTIC RESONATORS FOR MICROPHONES
    Publication number: 20230239611
    Abstract: Aspects of the subject technology relate to electronic devices having microphones. An electronic device may include a microphone and a resonator for the microphone. The resonator may be formed in a device structure that is spatially separated from the microphone. The resonator may be formed in an interior wall of a housing of the electronic device, or in a support structure within an enclosure of the electronic device. A resonator and/or one or more damping features, may reduce a resonance effect, on the microphone, of a resonant cavity within the enclosure of the electronic device and adjacent the microphone.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Inventors: Justin D. Crosby, Kevin M. FROESE, Tzu Hung Huang
  • ACOUSTIC RESONATORS FOR MICROPHONES
    Publication number: 20230239610
    Abstract: Aspects of the subject technology relate to electronic devices having microphones. An electronic device may include a microphone and a resonator for the microphone. The resonator may be formed in a device structure that is spatially separated from the microphone. The resonator may be formed in an interior wall of a housing of the electronic device, or in a support structure within an enclosure of the electronic device. A resonator and/or one or more damping features, may reduce a resonance effect, on the microphone, of a resonant cavity within the enclosure of the electronic device and adjacent the microphone.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 27, 2023
    Inventors: Justin D. Crosby, Kevin M. FROESE, Tzu Hung Huang