Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.

Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed during a fabrication of each of the workpiece products; performing photography on each of the melt pools on the powder bed during the fabrication of each of the workpiece products; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed; performing photography on each of the melt pools on the powder bed; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; first converting each of the workspace images to a gray level co-occurrence matrix (GLCM); building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.

Abstract: Embodiments of systems and methods for detecting short circuits in a load are described. In an illustrative, non-limiting embodiment, a short circuit detection system includes a first circuit, a second circuit, and a controller. The first circuit has an output and an input coupled to a load and an auxiliary power source through a resistor, while the second circuit is configured to enable an output of the short circuit detection circuit for a specified period of time following application of auxiliary power at the auxiliary power source. The controller includes computer-executable instructions to monitor the output of the first circuit, and allow or disallow a main power source from powering the load based upon whether a short circuit condition exists.

Abstract: Disclosed herein are peptide fragments of Amuc_1100* and the use thereof. The peptide is shown to be a ligand to activate TLR2 and is used to treat obesity and the related disease or condition. The peptide of the present invention is further used in the treatment of intestinal cancer, promoting immune response, and intestinal epithelial barrier dysfunction.

Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

Abstract: A light emitting diode (LED) and a light purification method therefor are provided, which belong to the technical field of LED. The LED includes an epitaxial structure and a light purification layer plated on the epitaxial structure. The light purification layer includes a first reflection layer and defines multiple light-exiting holes. The first reflection layer is plated on the epitaxial structure. The multiple light-exiting holes each extend through the first reflection layer and have an aperture which is N times a preset wavelength of an exit light, N being an integer and N?1.

Abstract: An anti-theft plastic bottle cap contains a body and an anti-theft ring. The body is connected on an opening of a bottle. The anti-theft ring is mounted on a bottom of the body, and multiple equidistant connection teeth are formed between the body and the anti-theft ring. The body includes a first protrusion extending to the anti-theft ring from a bottom of the body, and the anti-theft ring includes two second protrusions extending to the body. The first protrusion is engaged with the two second protrusions when the body is rotated clockwise, such that the anti-theft plastic bottle cap is not rotated overly by using the first protrusion and the two second protrusions to avoid a removal of the anti-theft ring from the body and the anti-theft ring before a user detaches the anti-theft plastic bottle cap from the bottle.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

Abstract: An orientation-adjustment mechanism is provided, which is adapted to be affixed to a mounting surface. The orientation-adjustment mechanism includes a base, a rod, a joint unit, and a mounted member. The base is adapted to be affixed to the mounting surface. The rod includes a first section and a second section. The first section of the rod pivots on the base. The joint unit is disposed on the second section of the rod. The joint unit includes a plurality of joint-positioning portions. The joint-positioning portions include a first joint-positioning portion and a second joint-positioning portion. The mounted member is connected to the joint unit and is adapted to be rotated relative to the joint unit. The mounted member includes a member housing. The member housing includes at least one member-positioning portion.

Abstract: A bus system is provided. A memory device is electrically connected to a master device via a serial peripheral interface (SPI) bus. A plurality of slave devices are electrically connected to the master device via an enhanced SPI (eSPI) bus. Each of the slave devices has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. The first slave device is electrically connected to the memory device via the SPI bus. After obtaining a program code from the memory device, the first slave device verifies the program code using a security code and controls the alert-handshake control line to unlock all the slave devices except for the first slave device via the alert handshake pin in response to the program code being verified. The unlocked slave devices communicate with the master device via the eSPI bus.

Abstract: Embodiments of systems and methods for detecting short circuits in a load are described. In an illustrative, non-limiting embodiment, a short circuit detection system includes a first circuit, a second circuit, and a controller. The first circuit has an output and an input coupled to a load and an auxiliary power source through a resistor, while the second circuit is configured to enable an output of the short circuit detection circuit for a specified period of time following application of auxiliary power at the auxiliary power source. The controller includes computer-executable instructions to monitor the output of the first circuit, and allow or disallow a main power source from powering the load based upon whether a short circuit condition exists.

Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.

Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.