Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.

Abstract: A motor control device and a motor control method are provided. The motor control device includes a memory and a controller. During an initialization period, the controller drives a brushless DC motor to change a rotor position through a drive circuit for adjusting and obtaining a starting angle and a locked exciting current corresponding to the starting angle, and the controller stores starting-angle information corresponding to the starting angle and locked exciting-current information corresponding to the locked exciting current in the memory. After the initialization period ends, during a normal rotation period, the controller maintains the rotor position of the brushless DC motor at the starting angle with the locked exciting current through the drive circuit, until the controller activates the brushless DC motor through the drive circuit.

Abstract: A light guide assembly includes a housing element, at least one light guide element, and at least one light-shielding element. The housing element includes an outer surface and an inner surface. The light guide element is configured for a light to pass therethrough. The light guide element includes a light entrance surface, at least one light exit surface, and at least one wall surface. The wall surface surrounds and is connected to an edge of the light exit surface and extends toward the light entrance surface. The light exit surface is in contact with the inner surface. The at least one light-shielding element surrounds the at least one wall surface and is in contact with the inner surface.

Abstract: A power ground noise reduction system includes a bandgap circuit and a noise reduction circuit. The bandgap circuit includes an input terminal for receiving a working voltage, and an output terminal for outputting a bandgap reference voltage. The noise reduction circuit includes a first input terminal coupled to the output terminal of the bandgap circuit for receiving the bandgap reference voltage, a second input terminal for receiving the working voltage, a ground terminal coupled to a low voltage terminal, a first current source for receiving the working voltage received by the second input terminal and generating a first current, and a second current source for generating a second current to the low voltage terminal through the ground terminal.

Abstract: Some implementations are directed to a wireless receiver. In some implementations, the wireless receiver may include a receiver body encompassing one or more antenna elements, a cover removably coupled to the receiver body, and a mounting bracket removably coupled to the receiver body. In some implementations, at least one of the one or more antenna elements, the cover, or the mounting bracket is movable with respect to the receiver body in order to align the wireless receiver with a signal path.

Abstract: A clock generating circuit includes an input terminal, configured to receive a clock signal; an output terminal, configured to output an output signal; a gray counter circuit, coupled to the input terminal, and configured to divide the clock signal to produce a first output signal; and a shielding circuit, coupled to the input terminal, the gray counter circuit and the output terminal, and configured to shield a glitch in the first output signal to generate the output signal according to the clock signal.

Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.

Abstract: A clock generating circuit includes an input terminal, configured to receive a clock signal; an output terminal, configured to output an output signal; a gray counter circuit, coupled to the input terminal, and configured to divide the clock signal to produce a first output signal; and a shielding circuit, coupled to the input terminal, the gray counter circuit and the output terminal, and configured to shield a glitch in the first output signal to generate the output signal according to the clock signal.

Abstract: A conductor layer is positioned between a gate electrode and a drain electrode. The conductor layer contacts a nitride semiconductor layer. The conductor layer is electrically connected with the drain electrode. The drain electrode includes a first part contacting the nitride semiconductor layer, and a second part positioned further toward the conductor layer side than the first part in a first direction. An insulating film includes a portion positioned between the conductor layer and the drain electrode. The second part is located on the portion of the insulating film.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a conductive part, an insulating part, and a third electrode. The second semiconductor layer is located on the first semiconductor layer. The first electrode is located on the second semiconductor layer. The first electrode includes an electrode part and an electrode extension part. The electrode part contacts the second semiconductor layer. The electrode extension part extends from an upper end portion of the electrode part. The conductive part is positioned between the first electrode and the second electrode. The conductive part contacts an upper surface of the second semiconductor layer and contacting the first electrode. The insulating part is located on the conductive part and is positioned between the conductive part and the electrode extension part.

Abstract: A layout method, a non-transitory computer-readable medium, and an associated integrated circuit are provided. The non-transitory computer-readable medium records a software program for performing the layout method of the integrated circuit having Q circuit blocks. The layout method includes the following steps. K gate-controlled elements and (K?1) buffers are placed on the edge of a qth circuit block. The K gate-controlled elements are connected between a supply voltage terminal and the qth circuit block. (K?1) gate-controlled elements, including an SEL[1]-th gate-controlled element, are selected as (K?1) source nodes. Another (K?1) gate-controlled elements, other than the SEL[1]-th gate-controlled element, are selected as (K?1) destination nodes. The (K?1) buffers are routed as (K?1) delayed gating lines connected between the (K?1) source nodes and the (K?1) destination nodes.

Abstract: A semiconductor device according to an embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; and a first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer.

Abstract: A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.

Abstract: A computing system is provided. The computing system a central processing unit (CPU) configured to run a basic input/output system (BIOS) service and an operating system (OS). The computing system further includes a baseboard management controller (BMC) and a first boot non-volatile memory coupled to both the CPU and the BMC. A first portion of the first boot non-volatile memory stores system settings and configuration in an open standard such that the BIOS and the BMC can access the system settings based on a temporal ownership of the first portion of the first boot non-volatile memory.

Abstract: A dual-chamber pressure control method and a dual-chamber pressure control device are described. The dual-chamber pressure control method uses a stepped pressure adjustment to ensure that the pressure adjustment at each stage will not exceed a safe value of an internal chamber body. The dual-chamber pressure control device includes a dual-chamber member, an external chamber pressure control module, and an internal chamber pressure control module. The external chamber pressure control module is used to adjust an external chamber pressure of the dual-chamber member, such that an external chamber pressure value changes with time to show a stepped external chamber pressure adjustment line. The internal chamber pressure control module is used to adjust an internal chamber pressure of the dual-chamber member, such that an internal chamber pressure value changes with time to show a stepped internal chamber pressure adjustment line.

Abstract: A semiconductor high pressure annealing device is described. The semiconductor high pressure annealing device includes a chamber body, a cover, a lifting mechanism, and a floating sealing structure. Air tightness between the chamber body and the cover is achieved by the floating sealing structure. A first sealing ring and a second sealing ring of the floating sealing structure are arranged on the top and the bottom for reducing the damage to the first sealing ring and the second sealing ring when the cover moves up and down. A preload spring assembly of the floating sealing structure can provide tension to assist in improving the air tightness between the chamber body and the cover.

Abstract: A vertical dual-chamber annealing device is provided. The vertical dual-chamber annealing device includes an outer chamber unit, an inner chamber body, a temperature control unit, a supporting structure, and a gas-tight seal structure. The inner chamber body can be moved upward, such that the inner chamber body can be located in the outer chamber unit and supported by the supporting structure. After the supporting of the supporting structure is removed, the inner chamber body is moved downward and separated from the outer chamber unit. Therefore, an arrangement of the inner chamber body and the outer chamber unit can increase the convenience of cleaning and replacing the inner chamber body. The structure of the inner chamber body can enhance the uniformity of a reaction temperature. The gas-tight seal structure isolates an inert gas and a reactive gas, which is beneficial to the recovery and the reuse of the reactive gas.

Abstract: A semiconductor device of an embodiment includes: a semiconductor layer including an element region and an element isolation region; a first insulation film provided on the semiconductor layer; a first electrode provided on the first insulation film and extending in a first direction; a second electrode provided on the semiconductor layer, arranged in a second direction intersecting with the first direction, and extending in the first direction; a third electrode provided on the semiconductor layer, arranged in the second direction, and extending in the first direction; second insulation films provided between the first insulation film and the semiconductor layer, and interposing the third electrode in the second direction; a first field plate electrode provided on the first electrode and connected to the first electrode; a second field plate electrode provided on the first field plate electrode and connected to the second electrode; and a third field plate electrode provided on the third electrode and connec

Abstract: The present disclosure provides GLP-1R agonists, and compositions, methods, and kits thereof. Such compounds are generally useful for treating a GLP-1R mediated disease or condition in a human.