Patents by Inventor Hung Hung

Hung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11262401
    Abstract: A wafer probe station includes a thermal chuck, a chuck stage, a platen, some probes, a first focusing device, a second focusing device and a thermal plate. The thermal chuck heats up to an operational temperature and holds a device under test (DUT). The chuck stage connects with the thermal chuck and moves the thermal chuck. The thermal chuck locates between the chuck stage and the platen. The probes are disposed on the platen and configured to contact with the DUT. The first focusing device is disposed on the platen to focus on the DUT. The second focusing device is disposed on the chuck stage to focus on the probes. The thermal plate locates between the second focusing device and the platen and is configured to heat up to the operational temperature. The thermal plate has a through hole aligning with the second focusing device.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: March 1, 2022
    Assignee: MPI Corporation
    Inventors: Stojan Kanev, Chia-Hung Hung
  • Patent number: 11251298
    Abstract: A semiconductor device of an embodiment includes: a first nitride semiconductor layer of a first conductive type; a second nitride semiconductor layer which is the first conductive type and is provided on the first nitride semiconductor layer; a third nitride semiconductor layer which is a second conductive type and is provided on the second nitride semiconductor layer; a fourth nitride semiconductor layer which is the first conductive type and is provided on the third nitride semiconductor layer; and a first electrode provided in a trench provided in the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride semiconductor layer, via a first insulating film.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 15, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yasuhiro Isobe, Hung Hung, Masaaki Onomura
  • Patent number: 11251406
    Abstract: The invention relates to a light extraction substrate having a light extraction layer. The light extraction layer includes boron, boroate, and/or borosilicate as well as nanoparticles.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 15, 2022
    Assignee: Vitro Flat Glass LLC
    Inventor: Cheng-Hung Hung
  • Publication number: 20220039208
    Abstract: An electrical connecting portion for a device with a heating function is a portion of a heating unit of the device. The electrical connecting portion includes a substrate, two copper layers, and two electrically conductive coating layers. The substrate is made of a light-transmittable material and includes a front face and a rear face. Each of the two copper layers includes at least one first through-hole extending in a front-rear direction. Each of the two electrically conductive coating layers substantially covers a respective one of the two copper layers and is coupled to the front face of the substrate. Each of the two electrically conductive coating layers substantially fills the at least one first through-hole of the respective one of the two copper layers. The two electrically conductive coating layers have an insulating spacing therebetween. Thus, the electrical connecting portion prevents hot melting and provides better electrical connection reliability.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Inventor: Jui-Hung Hung
  • Patent number: 11232157
    Abstract: A text comparison method is adapted for comparing a query file with an existing file. The text comparison method includes: converting the existing file, by an irreversible method, to obtain a first intermediate file, wherein the first intermediate file includes a plurality of characters, and a number of different characters of the plurality of characters is a predetermined value; receiving a second intermediate file which is a file converted from the query file by the irreversible method; and according to a predetermined string length, comparing the second intermediate file with the first intermediate file by a high repeating-character comparison method to output a comparison result. Therefore, the second intermediate file can be created offline and then only the second intermediate file but not the original query file is submitted through internet for private text comparison.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: January 25, 2022
    Assignees: NATIONAL TSING HUA UNIVERSITY, NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Lee-Wei Yang, Jui-Hung Hung, Emmanuel Oluwatobi Salawu, Yuan-Yu Chang
  • Publication number: 20220017955
    Abstract: A portable genome sequencing and genotyping device includes a sample processing module, a sequencing module, an analyzing module, and a communication module. The sample processing module is configured to process a sample so as to generate at least one DNA segment of the sample. The sequencing module is connected to the sample processing module, and is configured to generate a number of base sequences corresponding to the at least one DNA segment. The analyzing module is coupled to the sequencing module, and is configured to generate a genotyping analysis result based on the base sequences. The communication module is configured to receive the genotyping analysis result and transmit the genotyping analysis result to a user terminal.
    Type: Application
    Filed: December 7, 2020
    Publication date: January 20, 2022
    Inventors: Jui-Hung HUNG, Chia-Hsiang YANG
  • Patent number: 11213848
    Abstract: A nanoparticle coater includes a housing; a nanoparticle discharge slot; a first combustion slot; and a second combustion slot.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 4, 2022
    Assignee: Vitro Flat Glass LLC
    Inventors: James W. McCamy, Cheng-Hung Hung, Mehran Arbab, Abhinav Bhandari
  • Publication number: 20210359863
    Abstract: A method for creating a hierarchical threshold signature digital asset wallet using a hierarchical distributed key generator (DKG) and a signature protocol includes steps of generating a public key by users and the digital asset wallet service platform, securing and controlling a portion of shares, sending a transaction signing request, validating the transaction signing request, creating a signature of the signed transaction, and uploading the signed transaction to the corresponding digital asset blockchain network and monitoring the execution of the signed transaction.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 18, 2021
    Inventor: Chiu Hung Hung
  • Publication number: 20210333322
    Abstract: A wafer probe station includes a thermal chuck, a chuck stage, a platen, some probes, a first focusing device, a second focusing device and a thermal plate. The thermal chuck heats up to an operational temperature and holds a device under test (DUT). The chuck stage connects with the thermal chuck and moves the thermal chuck. The thermal chuck locates between the chuck stage and the platen. The probes are disposed on the platen and configured to contact with the DUT. The first focusing device is disposed on the platen to focus on the DUT. The second focusing device is disposed on the chuck stage to focus on the probes. The thermal plate locates between the second focusing device and the platen and is configured to heat up to the operational temperature. The thermal plate has a through hole aligning with the second focusing device.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Inventors: Stojan KANEV, Chia-Hung HUNG
  • Publication number: 20210336879
    Abstract: Techniques configure a network to relay data from a node to a root device are described herein. In an example, one-hop neighbors of the node are determined and ranked according to link quality. The ranked neighbor nodes may be considered potential “parent nodes” of the node. The ranked nodes may be divided into a plurality of groups according to link quality. A parent node may be selected from among the “best” group of one-hop neighbor nodes and may be used to relay data for the node to and/or from the router or other device. The node continues to use the parent node at least until its ranking removes it from the best group or falls below a threshold value. After the ranking of the parent falls below such a prescribed threshold it may be replaced by selection of a replacement parent from the group of one-hop upstream neighbors having the best link quality.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 28, 2021
    Inventor: Viet-Hung Hung Nguyen
  • Publication number: 20210194475
    Abstract: Provided is a semiconductor device including: a normally-off transistor having a first electrode, a second electrode, and a first control electrode; a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode; a first capacitor having a first end and a second end electrically connected to the second control electrode; a Zener diode having a first anode and a first cathode, the first anode being electrically connected to the second end and the second control electrode, and the first cathode being electrically connected to the third electrode; a first resistor having a third end and a fourth end electrically connected to the first control electrode; a first diode having a second anode and a second cathode, the second anode being electrically connected to the third end; a second resistor having a fifth end electrically connected to the second cathode and a sixth end electrically connected to the fourth end and the first cont
    Type: Application
    Filed: September 4, 2020
    Publication date: June 24, 2021
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura, Hitoshi Kobayashi, Tetsuya Ohno
  • Patent number: 11014118
    Abstract: A float bath coating system includes at least one nanoparticle coater located in a float bath. The at least one nanoparticle coater includes a housing, a nanoparticle discharge slot, a first combustion slot, and a second combustion slot. The nanoparticle discharge slot is connected to a nanoparticle source and a carrier fluid source. The first combustion slot is connected to a fuel source and an oxidizer source. The second combustion slot is connected to a fuel source and an oxidizer source.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 25, 2021
    Assignee: Vitro Flat Glass LLC
    Inventors: James W. McCamy, Cheng-Hung Hung, Mehran Arbab, Abhinav Bhandari
  • Publication number: 20210148506
    Abstract: A bracket structure is provided. The bracket structure includes a base, a connection pipe and at least one cascade member. The base includes a base body, a first connection protrusion and a second connection protrusion. The first connection protrusion and the second connection protrusion are affixed to the base body. The first connection protrusion includes a first contact surface. The second connection protrusion includes a second contact surface. The first contact surface faces the second contact surface. The connection pipe includes an extending section, a fitting section and a pivot section. The cascade member pivots on the first connection protrusion, the pivot section and the second connection protrusion. The pivot section includes a first abutting surface and a second abutting surface. The first abutting surface forms a surface-to-surface contact with the first contact surface. The second abutting surface forms a surface-to-surface contact with the second contact surface.
    Type: Application
    Filed: September 2, 2020
    Publication date: May 20, 2021
    Inventors: Lan-Chun YANG, Yi-Chieh LIN, Ming-Hung HUNG, Chun-Wei WANG
  • Publication number: 20210148539
    Abstract: A vehicle lamp includes a housing including a compartment having an opening. A reflective unit and a lighting unit are mounted in the compartment. The lighting unit includes a first circuit board and a first LED. A lens is mounted to a front end of the housing and covers the opening of the compartment. The reflective unit reflects light rays from the first LED to transmit through the lens. A heating unit includes a substrate made of a light transmittable material and a heating layer disposed on the substrate. A sensor is mounted in the compartment for detecting temperature. When the detected temperature is lower than a first predetermined temperature, the heating layer is activated to proceed with an electrical heating operation. When the detected temperature is higher than a second predetermined temperature, the electrical heating operation of the heating layer is stopped or gradually reduced.
    Type: Application
    Filed: December 18, 2019
    Publication date: May 20, 2021
    Inventors: Ming-Hung Ting, Jui-Hung Hung
  • Publication number: 20210134864
    Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Patent number: 10998433
    Abstract: A semiconductor device of an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer placed on the first nitride semiconductor layer; a first electrode placed on the second nitride semiconductor layer; a second electrode placed on the first nitride semiconductor layer; a gate electrode placed between the first electrode and the second electrode; a first field plate electrode placed on the second nitride semiconductor layer, the first field plate electrode having the same height as the gate electrode; and a second field plate electrode provided on an upper side of the first field plate electrode, the second field plate electrode being placed on a side of the second electrode compared to the first field plate electrode.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hung Hung, Yasuhiro Isobe, Akira Yoshioka, Toru Sugiyama, Masaaki Iwai, Naonori Hosokawa, Masaaki Onomura
  • Publication number: 20210083577
    Abstract: A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by Vth, a maximum rated gate voltage of the normally-off transistor is denoted by Vg_max, a voltage of the fourth end portion is denoted by Vg_on, the first capacitance component is deno
    Type: Application
    Filed: January 17, 2020
    Publication date: March 18, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira YOSHIOKA, Toru SUGIYAMA, Masaaki IWAI, Naonori HOSOKAWA, Masaaki ONOMURA, Hung HUNG, Yasuhiro ISOBE
  • Publication number: 20210083102
    Abstract: A semiconductor device of an embodiment includes: a first nitride semiconductor layer of a first conductive type; a second nitride semiconductor layer which is the first conductive type and is provided on the first nitride semiconductor layer; a third nitride semiconductor layer which is a second conductive type and is provided on the second nitride semiconductor layer; a fourth nitride semiconductor layer which is the first conductive type and is provided on the third nitride semiconductor layer; and a first electrode provided in a trench provided in the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride semiconductor layer, via a first insulating film.
    Type: Application
    Filed: February 25, 2020
    Publication date: March 18, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yasuhiro ISOBE, Hung Hung, Masaaki Onomura
  • Patent number: 10937819
    Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 2, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Patent number: 10922071
    Abstract: A centralized flash memory module is provided. The centralized flash memory module includes flash memory components, a flash memory management controller (FMMC), and a complex programmable logic device (CPLD). Each of the flash memory components is connected to a server device separate from the centralized flash memory module. The FMMC is configured to connect to the flash memory components and to a rack management device, separate from the centralized flash memory module. The CPLD is configured to connect the FMMC to the flash memory components and connect the server device to the flash memory components.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: February 16, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ming-Hung Hung, Hsin-Hung Kuo, Chin-Fu Ou