Patents by Inventor Hung-Jen Liao

Hung-Jen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9997219
    Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Publication number: 20180158510
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Publication number: 20180151226
    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 31, 2018
    Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Hsien-Yu PAN, Chih-Yu LIN, Yen-Huei CHEN, Chien-Chen LIN
  • Patent number: 9979399
    Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Che-Ju Yeh
  • Publication number: 20180130809
    Abstract: A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Inventors: Yen-Huei CHEN, Hung-Jen LIAO, Chih-Yu LIN, Jonathan Tsung-Yung CHANG, Wei-Cheng WU
  • Patent number: 9959916
    Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 1, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jonathan Tsung-Yung Chang, Chiting Cheng, Cheng Hung Lee, Hung-Jen Liao, Michael Clinton
  • Publication number: 20180096710
    Abstract: A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 5, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20180090183
    Abstract: In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9922701
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 9922700
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Publication number: 20180053537
    Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Chien-Kuo SU, Cheng Hung LEE, Chiting CHENG, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Pankaj AGGARWAL, Jhon Jhy LIAW
  • Publication number: 20180040366
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Mahmut Sinangil, Chiting Cheng, HUNG-JEN LIAO, Tsung-Yung Chang
  • Patent number: 9886996
    Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Patent number: 9865605
    Abstract: A memory circuit includes a first column of memory cells arranged along a first direction, a first supply voltage line extending along the first direction in a first conductive layer of the memory circuit, a second supply voltage line, a first resistive device electrically connecting the first supply voltage line and the second supply voltage line, and a supply voltage source. Each memory cell of the first column of memory cells includes a supply voltage line segment. The first supply voltage line is made of at least the supply voltage line segments of the first column of memory cells. The supply voltage source is electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device is in a lowest resistance path of the one or more conductive paths.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • Patent number: 9853035
    Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9842627
    Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 9837130
    Abstract: In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20170344696
    Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to eliminate a false path of the circuit unit in the second electronic list based on the net information output.
    Type: Application
    Filed: December 2, 2016
    Publication date: November 30, 2017
    Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
  • Publication number: 20170345485
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Application
    Filed: May 24, 2016
    Publication date: November 30, 2017
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Patent number: 9824729
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw