Patents by Inventor Hung-Jen Liao

Hung-Jen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170084317
    Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.
    Type: Application
    Filed: October 27, 2015
    Publication date: March 23, 2017
    Inventors: JONATHAN TSUNG-YUNG CHANG, CHITING CHENG, CHENG HUNG LEE, HUNG-JEN LIAO, MICHAEL CLINTON
  • Patent number: 9601162
    Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20170076755
    Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.
    Type: Application
    Filed: May 12, 2016
    Publication date: March 16, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Patent number: 9589885
    Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Jen Liao, Jung-Hsuan Chen, Chien Chi Tien, Ching-Wei Wu, Jui-Che Tsai, Hong-Chen Cheng, Chung-Hsing Wang
  • Publication number: 20170047333
    Abstract: A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 16, 2017
    Inventors: Tsung-Hsien HUANG, Hong-Chen CHENG, Cheng Hung LEE, Hung-Jen LIAO
  • Patent number: 9552873
    Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Kuei Lin, Hung-Jen Liao, Yen-Huei Chen
  • Patent number: 9536598
    Abstract: Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation or write operation. The memory arrangement comprises a word-line driver comprising at least a first input terminal and a second input terminal. The first input terminal is operably coupled to a first decoder and the second input terminal is operably coupled to a second decoder. When the word-line driver senses a first voltage at the first input terminal and a second voltage at the second input terminal, the word-line driver outputs a gate voltage signal which activates the memory cell.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limi
    Inventors: Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20160372181
    Abstract: A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventors: Hidehiro FUJIWARA, Li-Wen WANG, Yen-Huei CHEN, Hung-Jen LIAO
  • Publication number: 20160351252
    Abstract: A circuit includes: a first word line; a second word line; and a memory cell. The memory cell includes: a first pass gate, between a transistor and a first data line (RBL), having a gate coupled to the first word line; the transistor having a drain coupled to the first pass gate, a source coupled to a reference node, and a gate coupled to a data node of the memory cell; and a second pass gate, between the data node and a second data line, having a gate coupled to the second word line. The first word line is configured to turn on the first pass gate. The second word line is configured to turn on the second pass gate after an elapse of a first delay.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 1, 2016
    Inventors: Hidehiro FUJIWARA, Kao-Cheng LIN, Yen-Huei CHEN, Hung-Jen LIAO
  • Patent number: 9496026
    Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: November 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mohammed Hasan Taufique, Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen
  • Publication number: 20160322098
    Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Mohammed HASAN TAUFIQUE, Hidehiro FUJIWARA, Hung-Jen LIAO, Yen-Huei CHEN
  • Patent number: 9484350
    Abstract: A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Huang, Hong-Chen Cheng, Cheng-Hung Lee, Hung-Jen Liao
  • Publication number: 20160284387
    Abstract: An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: Yen-Huei CHEN, Hung-Jen LIAO, Chih-Yu LIN, Jonathan Tsung-Yung CHANG, Wei-Cheng WU
  • Publication number: 20160276019
    Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.
    Type: Application
    Filed: July 18, 2014
    Publication date: September 22, 2016
    Inventors: Tzu-Kuei LIN, Hung-Jen LIAO, Yen-Huei CHEN, Ching-Wei WU
  • Patent number: 9449667
    Abstract: A memory circuit includes a plurality of memory cells arranged into columns and one or more pairs of adjacent rows and one or more first word lines. Each memory cell of the plurality of memory cells includes a data node, a first access node, and a first pass gate coupled to the first access node and configured to selectively alter a voltage level at the first access node according to a voltage level at the data node if the first pass gate is turned on. A word line of the one or more first word lines is coupled with the first pass gates of a pair of the one or more pairs of adjacent rows, and the first pass gates of the pair of the one or more pairs of adjacent rows are configured to be selectively turned on responsive to a voltage level at the word line.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9425095
    Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
    Type: Grant
    Filed: May 24, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
  • Patent number: 9418729
    Abstract: A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9412742
    Abstract: A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Ming-Yi Lee, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20160163380
    Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 9, 2016
    Inventors: Tzu-Kuei LIN, Hung-Jen LIAO, Yen-Huei CHEN
  • Publication number: 20160148676
    Abstract: A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.
    Type: Application
    Filed: February 2, 2016
    Publication date: May 26, 2016
    Inventors: Wei-Cheng WU, Wei Min CHAN, Yen-Huei CHEN, Hung-Jen LIAO, Ping-Wei WANG