Patents by Inventor Hung Liao

Hung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818515
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Patent number: 10818675
    Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. A first SRAM cell is adjacent to a second SRAM cell in the same row. A third SRAM cell is adjacent to the first SRAM cell in the same column. A fourth SRAM cell is adjacent to the second SRAM in the same column. A contact plug is positioned between the first, second, third and fourth SRAM cells. A VSS line is electrically coupled to the first, second, third and fourth SRAM cells through the contact plug. The contact plug is free of the barrier layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Hsieh, Yu-Min Liao, Jhon-Jhy Liaw
  • Publication number: 20200335694
    Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 22, 2020
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Publication number: 20200334338
    Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.
    Type: Application
    Filed: July 22, 2019
    Publication date: October 22, 2020
    Applicant: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Yuan-Hung Liao, Chih-Chen Liu
  • Patent number: 10811423
    Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
  • Patent number: 10811300
    Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Patent number: 10801489
    Abstract: A gas transportation device includes a gas outlet cover, at least one flow-guiding pedestal, a primary gas pump, a secondary gas pump and an adhesive film. The gas outlet cover includes a gas outlet nozzle and a gas outlet cavity. Each flow-guiding pedestal includes a main plate, a protruding frame and a chamber frame. The main plate includes a recess and a communicating aperture. The primary gas pump is disposed in the protruding frame, and the secondary gas pump is disposed in the chamber frame. The adhesive film has a hollow structure, is disposed between the primary gas pump and the flow-guiding pedestal and defines a convergence chamber. Consequently, the gas is introduced into the recess, transported to the primary gas pump through the communicating apertures and the convergence chamber, transported to the gas outlet cavity via the primary gas pump, and finally discharged out from the gas outlet nozzle.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 13, 2020
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Shou-Hung Chen, Chi-Feng Huang, Chang-Yen Tsai
  • Patent number: 10795335
    Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 6, 2020
    Assignee: NIKE, Inc.
    Inventors: Dragan Jurkovic, Patrick Conall Regan, Chih-Chi Chang, Chang-Chu Liao, Ming-Feng Jean, Kuo-Hung Lee, Yen-Hsi Liu, Hung-Yu Wu
  • Patent number: 10792697
    Abstract: A drippage prevention system including: a first automatic control valve (ACV), an input of the first ACV fluidically connected to a source of fluid to be dispensed, the first ACV having a position ranging from fully closed to fully open; a second ACV, an input of the second ACV being fluidically connected to the output of the first ACV, and an output of the second ACV being fluidically connected to a nozzle, the second ACV having positions ranging from fully closed to fully open; a proxy sensor configured to generate a proxy signal representing an indirect measure of a position of the first ACV; and a controller electrically connected to the first and second ACVs and the proxy sensor, the controller being configured to cause the second ACV to close based on the proxy signal and thereby stop flow of the liquid to the nozzle.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hung Wang, Chun-Chih Lin, Chi-Hung Liao, Yung-Yao Lee, Wei Chang Cheng
  • Patent number: 10796759
    Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Patent number: 10788740
    Abstract: A projector and its illumination system and wavelength conversion device are provided. The wavelength conversion device includes a substrate, a wavelength converting portion, and a wavelength maintaining portion. The substrate has a rotation axis. The wavelength converting portion surrounds the rotation axis and is adapted to receive the first beam and convert a first portion of the first beam into a second beam. The wavelength maintaining portion surrounds the rotation axis and is adapted to receive the first beam and guide a second portion of the first beam. A ratio of the first portion of the first beam with respect to the first beam is greater than a ratio of the second portion of the first beam with respect to the first beam. The illumination system and the wavelength conversion device in the projector reduce the number of optical elements, thereby reducing the cost and the size of the projector.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 29, 2020
    Assignee: Coretronic Corporation
    Inventors: Chien-Chung Liao, Jen-Hung Huang, Kuan-Ta Huang
  • Publication number: 20200303214
    Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Publication number: 20200301292
    Abstract: A system includes a frame, a projection lens, a wafer table, and a cleaner. The frame has an opening vertically extending through the frame. The projection lens is disposed on the frame. The wafer table is below the frame, in which the wafer table is movable along a horizontal direction. The cleaner is over the frame, in which the cleaner comprises a sticky structure movable along a vertical direction and through the opening of the frame.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Cheng WU, Chi-Hung LIAO
  • Publication number: 20200303394
    Abstract: Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 24, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Wen Hung, Yu-Kai Liao, Chiang-Hung Chen
  • Publication number: 20200303118
    Abstract: A method to form a plurality of inductors in a single process by placing multiple coils on a first magnetic sheet, and then stacking magnetic layers on the first magnetic sheet to encapsulate the coils so as to from a large magnetic body, and then cutting the large magnetic body into multiple inductors, wherein a terminal part of the coil disposed on the bottom surface of the magnetic body of the inductor is extended away from the axis of the coil and is entirely located at a same side of the axis of the coil.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 24, 2020
    Inventors: Chin Hung Wei, Min Lian Kuo, Chung Kai Liao
  • Publication number: 20200303213
    Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Publication number: 20200294821
    Abstract: A post CMP cleaning apparatus is provided. The post CMP cleaning apparatus includes a cleaning stage. The post CMP cleaning apparatus also includes a rotating platen disposed in the cleaning stage, and the rotating platen is configured to hold and rotate a semiconductor wafer. The post CMP cleaning apparatus further includes a vibrating device disposed over the rotating platen. The post CMP cleaning apparatus further includes a solution delivery module disposed near the vibrating device and configured to deliver a cleaning fluid to the semiconductor wafer. The vibrating device is configured to provide the cleaning fluid with a specific frequency which is at least greater than 100 MHz while the rotating platen is rotating the semiconductor wafer, so that particles on the semiconductor wafer are removed by the cleaning fluid.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Chen-Hao WU, Chu-An LEE, Chun-Hung LIAO, Shen-Nan LEE, Teng-Chun TSAI, Huang-Lin CHAO, Chih-Hung CHEN
  • Publication number: 20200292470
    Abstract: A photolithography method includes dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer; capturing an image of the first liquid on the first target layer; patterning the first target layer after capturing the image of the first liquid; comparing the captured image of the first liquid to a first reference image to generate a first comparison result; responsive to the first comparison result, positioning the nozzle and a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer; dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; and patterning the second target layer after dispensing the second liquid.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Chi-Hung Liao, Wei Chang Cheng
  • Publication number: 20200295791
    Abstract: A signal processing device includes a signal input, a signal output, a first amplifier, a second amplifier, a first distortion adjustment circuit, and a second distortion adjustment circuit. The signal input receives a RF signal to be amplified. The signal output outputs an amplified RF signal. Each of the first and second amplifiers includes an input coupled to the signal input and an output coupled to the signal output. The first distortion adjustment circuit includes a connection coupled to the input of the first amplifier. The second distortion adjustment circuit includes a connection coupled to the input of the second amplifier. The number of transistors in the first amplifier is different from the number of transistors in the second amplifier.
    Type: Application
    Filed: August 15, 2019
    Publication date: September 17, 2020
    Applicant: RichWave Technology Corp.
    Inventor: Lu-Hung Liao
  • Patent number: 10778086
    Abstract: A power source switching circuit for powering an electronic component includes a soft-start circuit, a first input connected to a standby power source, a second input connected to a main power source, and an output. The output provides a voltage to the electronic component and is configured to be alternatively electrically connected to the first input or the second input. When the power source switching circuit is in a standby mode, the output is connected to the first input and the standby power source. When the power source switching circuit is in a main mode, the output is connected to the second input and the main power source. When the power source switching circuit is initially activated to the standby mode, the soft-start circuit is enabled. When the power source switching circuit subsequently switched from the main mode to the standby mode, the soft-start circuit is disabled.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 15, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yu-Shin Liao, Kuo-Chan Hsu, Yun-Teng Shih, Cheng-Hung Yu