Abstract: A display system includes a display, a plurality of first sensor devices, and a system chip. The first sensor devices are configured to provide a plurality of detection signals. The system chip is electrically connected to the display and the first sensor devices. The system chip includes an image processor circuit, a central processor circuit, and a timing controller circuit. The image processor circuit is electrically connected to the first sensor devices. The image processor circuit is configured to analyze the detection signals. The central processor circuit is electrically connected to the image processor circuit. The central processor circuit is configured to generate an integrated command according to the analyzed plurality of detection signals. The timing controller circuit is electrically connected to the central processor circuit. The timing controller circuit is configured to drive the display to display an image according to the integrated command.

Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.

Abstract: An antenna device includes a substrate and four antenna units. The four antenna units are disposed on the substrate. Each of the four antenna units includes an L-shaped radiation portion, a hook-shaped coupling portion and a ground portion. The hook-shaped coupling portion is adjacent to the L-shaped radiation portion. The ground portion is disposed around the L-shaped radiation portion and the hook-shaped coupling portion. One end of the hook-shaped coupling portion is connected to the ground portion.

Abstract: An electronic device is provided. The electronic device includes at least one electronic circuit, a scan line, and a scan signal conversion circuit. The scan line transmits a first scan signal. The scan signal conversion circuit is electrically connected to the at least one electronic circuit and the scan line. The scan signal conversion circuit receives the first scan signal, converts the first scan signal into a second scan signal, and provides the second scan signal to the at least one electronic circuit.

Abstract: An electronic device including a circuit layer, an electronic element, a first flow-path structure and a fluid material is disclosed. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The first flow-path structure includes a first flow path, and the electronic element is disposed in the first flow-path structure. The fluid material is disposed in the first flow path. The fluid material is used for performing heat exchange with the electronic element. The circuit layer includes an input hole and an output hole, and the fluid material enters the first flow path through the input hole and exits the first flow path through the output hole.

Abstract: An icon display module includes a light blocking structure, a first light-emitting element, a second light-emitting element, a first light-guiding pattern structure and a second light-guiding pattern structure. The light blocking structure includes an accommodation space and a first light-blocking part. The accommodation space is divided into a first region and a second region by the first light-blocking part. When the first light-emitting element emits a first light beam, the first light beam is guided by the first light-guiding pattern structure and the second light-guiding pattern structure and projected on the target. Consequently, a first icon and a second icon are shown on the target. When the second light-emitting element emits a second light beam, the second light beam is guided by the first light-guiding pattern structure and projected to the target. Consequently, the first icon is shown on the target.

Abstract: The present disclosure relates to the technical field of medicaments. Particularly, the present disclosure provides a pharmaceutical combination/composition comprising a phosphodiesterase type 5 (PDE5) inhibitor, arginine, and N-acetylcysteine and its applications in treating cardiovascular diseases and erectile dysfunction.

Abstract: A keyswitch structure includes a keycap, a baseplate, a support mechanism including pivotally coupled first frame and second frame, a cam portion disposed on the keycap or the first frame, a restoring member providing a restoring force, and a sound-generating unit including a holder and a sound-generating member mounted on the holder. The first frame has a shaft hole defining a shaft rotatably coupled to the keycap. The sound-generating unit has an extending arm extending corresponding to an impact portion of the holder. In a plane view, the extending arm is located at an inner side of the first frame and an outer side of the inner edge of the shaft hole. When the keycap moves toward the baseplate, the cam portion presses the extending arm downward, and then the extending arm is released from the cam portion and bounces upward to hit the impact portion to generate a sound.

Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: An icon display module includes a light blocking structure, a first light-emitting element, a second light-emitting element, a first light-guiding pattern structure and a second light-guiding pattern structure. The light blocking structure includes an accommodation space and a first light-blocking part. The accommodation space is divided into a first region and a second region by the first light-blocking part. When the first light-emitting element emits a first light beam, the first light beam is guided by the first light-guiding pattern structure and the second light-guiding pattern structure and projected on the target. Consequently, a first icon and a second icon are shown on the target. When the second light-emitting element emits a second light beam, the second light beam is guided by the first light-guiding pattern structure and projected to the target. Consequently, the first icon is shown on the target.

Abstract: The present disclosure discloses a flow battery system, a battery monitoring device for the flow battery system, and an electrode element for the battery monitoring device and a manufacturing method thereof. The battery monitoring device includes a positive end plate, a positive electrode element, a negative end plate, a negative electrode element, electrolyte supply channels, electrolyte discharge channels, a separator, and a voltage measurement unit. The positive electrode element penetrates through the positive end plate and includes an electrode rod and a signal transmission portion that protrudes from an outer surface of the positive end plate. The negative electrode element penetrates through the negative end plate and includes an electrode rod and a signal transmission portion that is projected on an outer surface of the negative end plate. The separator is between the positive end plate and the negative end plate.

Abstract: A time synchronization method is provided for a time synchronization device, wherein the time synchronization device runs a plurality of precision time protocol (PTP) instances to connect to a plurality of time synchronization domains respectively. The time synchronization method includes determining whether a frequency of a local PTP clock of the time synchronization device is changed; and updating a frequency of a local clock of the time synchronization device with the frequency of the local PTP clock in response to the frequency of the local PTP clock being changed.

Abstract: The present disclosure provides a method of forming a capacitor. The method includes the following operations. A metal oxide insulating layer is formed on a first conductive layer with a first temperature, in which the first temperature is lower than a crystallization temperature of the metal oxide insulating layer. A second conductive layer is formed on the metal oxide insulating layer with a second temperature. An insulating layer is formed on the second conductive layer with a third temperature to crystallize the metal oxide insulating layer to form a crystallized metal oxide insulating layer, in which the second temperature is between the first temperature and the third temperature.

Abstract: A time synchronization method used for a time synchronization device is provided. The time synchronization device runs a plurality of Precision Time Protocol (PTP) instances to connect to a plurality of time synchronization domains through a plurality of ports. The time synchronization method includes selecting a grandmaster (GM) clock from the plurality of time synchronization domains; updating clock information of the grandmaster clock; determining whether each of the plurality of ports is a time receiving port or a time transmitting port according to the grandmaster clock; modifying clock attributes of each of the plurality of PTP instances according to whether the corresponding port is the time receiving port or the time transmitting port; and synchronizing, by the plurality of PTP instances, timings of the plurality of time synchronization domains according to the grandmaster clock.

Abstract: A transistor device includes a substrate and a transistor. The transistor is disposed on the substrate and includes a gate, a gate dielectric layer, a semiconductor layer, a source and a drain. The gate dielectric layer is disposed on the gate. The semiconductor layer is disposed on the gate dielectric layer, and includes a first region and a second region. The first region at least partially overlaps with the gate in a normal direction of the substrate, the second region extends from the first region to an edge of the semiconductor layer, and the second region further includes a dopant compared to the first region. The source and the drain are disposed on the semiconductor layer, and are electrically connected to the second region of the semiconductor layer. At least one of the source and the drain does not overlap with the gate in the normal direction of the substrate.

Abstract: An example of the present disclosure includes a packaging box, comprising a first section including a first aperture to receive a portion of a writing device, and a second section including a second aperture to receive a remainder of the writing device. The packaging box further includes a hinge mechanism coupling the first section to the second section, wherein the first section and second section are rotatable about the hinge mechanism. The packaging box also includes a tip remover including a surface to remove a tip of the writing device responsive to application of a force.

Abstract: A cleaning apparatus for cleaning a surface of a photomask includes a housing defining a chamber, a photomask holder disposed within the chamber, and a gas dispenser disposed within the chamber to direct gas toward the photomask holder. The gas dispenser has two or more gas dispensing outlets. A driver is coupled to at least one of the photomask holder or the gas dispenser to establish relative movement between the photomask holder and the gas dispenser.