Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

Abstract: A heat sink and an electronic device are provided. The electronic device includes a circuit board and a heat sink. The circuit board has a heat source, and the heat sink contacts the heat source to dissipate the heat. The heat sink includes a heat dissipating plate and a cover plate. The heat dissipating plate has an inlet region, an outlet region and a vaporization region between the inlet region and the outlet region. The vaporization region is disposed corresponding to the heat source. The cover plate covers on the heat dissipating plate, and a space between the cover plate and the heat dissipating plate forms a channel with an inlet and an outlet. A cooling liquid flows into the channel from the inlet, is vaporized to a gas while passing through the vaporization region, and the vaporized gas dissipates outside the channel through the outlet.

Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.

Abstract: A color conversion panel and a display device are provided. The color conversion panel includes an opaque substrate and a sapphire substrate. The opaque substrate includes a plurality of first pixel openings, a plurality of second pixel openings and a plurality of third pixel openings. The first pixel openings are filled with red quantum dot material, and the second pixel openings are filled with green quantum dot material. The sapphire substrate is on the opaque substrate. A first surface of the sapphire substrate that faces the opaque substrate has a plurality of first arc surfaces corresponding to the first pixel openings, a plurality of second arc surfaces corresponding to the second pixel openings, and a plurality of third arc surfaces corresponding to the third pixel openings.

Abstract: An annular optical element includes an outer annular surface, an inner annular surface, a first side surface, a second side surface and a plurality of strip-shaped wedge structures. The outer annular surface surrounds a central axis of the annular optical element and includes at least two shrunk portions. The first side surface connects the outer annular surface and the inner annular surface. The second side surface connects the outer annular surface and the inner annular surface, wherein the second side surface is disposed correspondingly to the first side surface. The strip-shaped wedge structures are disposed on the inner annular surface, wherein each of the strip-shaped wedge structures is disposed along a direction from the first side surface towards the second side surface and includes an acute end and a tapered portion connecting the inner annular surface and the acute end.

Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.

Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: An establishing method of semantic distance map for a moving device, includes capturing an image; obtaining a single-point distance measurement result of the image; performing recognition for the image to obtain a recognition result of each obstacle in the image; and determining a semantic distance map corresponding to the image according to the image, the single-point distance measurement result and the recognition result of each obstacle of in the image; wherein each pixel of the semantic distance map includes an obstacle information, which includes a distance between the moving device and an obstacle, a type of the obstacle, and a recognition probability of the obstacle.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.

Abstract: An information handling system includes a memory and a processor. The memory stores a current basic input/output system (BIOS) firmware image. During a regular boot mode of the information handling, the processor creates a first set of tables associated with the current BIOS firmware image, stores the first tables to the memory, and receives a BIOS firmware update image. During a BIOS update boot mode of the information handling system, the processor creates a second plurality of tables associated with the BIOS firmware update image, and compares the first and second tables. In response to a difference being determined between the first and second tables, the processor aborts the BIOS update boot mode and generate an error log.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: A method of manufacturing a light-emitting element, includes: providing a base having an upper surface and a lower surface; forming a semiconductor stack on the upper surface; removing part of the semiconductor stack to form a pre-defined dicing region surrounding the semiconductor stack; forming a dielectric stack covering the semiconductor stack and the pre-defined dicing region; and applying a first laser having a first wavelength to irradiate the base along the pre-defined dicing region; wherein the dielectric stack has a reflectance of 10%-50% and/or a transmittance of 50%-90% for the first wavelength.

Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.