Patents by Inventor Hung Lin

Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942699
    Abstract: An antenna device includes a first insulation layer, a defected metal layer, a second insulation layer, and a plurality of radiators. The defected metal layer is disposed on the first insulation layer, and the defected metal layer has a plurality of recess features which are arranged with uniform pitches. The second insulation layer is disposed on the first insulation layer and the defected metal layer. The radiators are disposed on the second insulation layer, and each radiator has a feeding portion and a grounding portion.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 26, 2024
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Hsin-Hung Lin, Wei Chen Cheng
  • Patent number: 11942433
    Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
  • Patent number: 11942570
    Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: March 26, 2024
    Assignee: CHONGQING KONKA PHOTOELECTRIC TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Kuo-Tung Huang, Ya-Wen Lin, Chia-Hung Huang
  • Patent number: 11941339
    Abstract: Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: March 26, 2024
    Assignee: Synopsys, Inc.
    Inventors: Linx Lin, Alex Tsai, Hung-Shih Wang
  • Patent number: 11942439
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Yung-Chang Lien
  • Publication number: 20240094834
    Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.
    Type: Application
    Filed: July 27, 2023
    Publication date: March 21, 2024
    Inventors: Shih-Yen LEE, Tzu-Yu TING, Yeh Sen-Fan CHUEH, Min-Hung LIN, Shih-Hsiung HSIAO
  • Publication number: 20240096289
    Abstract: The disclosure provides a control method of a display driver. The control method includes receiving address information and defining an IC address according to the address information. The IC address includes n bits representing k zones, and n and k are positive integers. The control method further includes receiving the IC address, a black frame data signal and a pulse-width modulation (PWM) signal, and turning on or off the plurality of LEDs in the corresponding zone according to toggle of bit in the black frame data signal. Each bit in the black frame data signal indicates that a plurality of LEDs in a zone among the k zones are turned on or off.
    Type: Application
    Filed: February 13, 2023
    Publication date: March 21, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Yi-Yang Tsai, Hung-Ho Huang, Tzong-Honge Shieh, Chieh-An Lin, Po-Hsiang Fang, Jhih-Siou Cheng
  • Publication number: 20240096781
    Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
  • Publication number: 20240094498
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Wei-Jhe SHEN, Shou-Jen LIU, Kun-Shih LIN, Yi-Ho CHEN
  • Publication number: 20240094559
    Abstract: A contact lens includes a central region, an annular region and a peripheral region. The central region includes a central point of the contact lens. The annular region symmetrically surrounds the central region. The peripheral region symmetrically surrounds the annular region. The peripheral region includes at least one color pattern portion. The annular region includes at least one power of critical point.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: En-Ping LIN, I-Wei LAI, Chun-Hung TENG
  • Publication number: 20240097351
    Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 21, 2024
    Inventors: Hsin Hung LIN, Yu Shu TAI, Wei Chen CHENG
  • Publication number: 20240096753
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a device area and a peripheral area surrounding the device area; a via, disposed at the peripheral area and extending at least partially through the substrate; an insulating structure, disposed at the peripheral area, extending at least partially through the substrate and surrounding the via; and a doped region, disposed at the peripheral area, over or in the substrate and adjacent to the via.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 21, 2024
    Inventors: Harry-Haklay Chuang, Shiang-Hung Huang, Hsin Fu Lin
  • Publication number: 20240098932
    Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.
    Type: Application
    Filed: July 19, 2023
    Publication date: March 21, 2024
    Applicant: Acer Incorporated
    Inventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
  • Publication number: 20240096787
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Ming-Da CHENG, Wei-Hung LIN, Hui-Min HUANG, Chang-Jung HSUEH, Po-Hao TSAI, Yung-Sheng LIN
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20240096830
    Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11936198
    Abstract: A wireless device is provided and includes a substrate, a first coil and a second coil. The first coil is configured to be wound around a first axis, and the first coil is disposed on the substrate and is configured to operate in a wireless charging mode. The second coil is disposed on the substrate and configured to operate in a wireless communication mode. The wires of the second coil partially overlap the wires of the first coil.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Feng-Lung Chien, Hsiang-Hui Hsu, Chien-Hung Lin
  • Patent number: 11933309
    Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, the signal value of the first driving signal gradually decreases until being equal to the signal value of the second driving signal. Wherein the signal value of the first driving signal non-linearly decreases, the signal value of the second driving signal is an unchanged value. Wherein, the first time period and the second time period are adjusted for a different fan but the sum of the first time period and the second time period is always the same. A fan is also disclosed.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Fan Lin, Chung-Hung Tang, Cheng-Chieh Liu, Chun-Lung Chiu