Abstract: An underwater robotic device includes a housing unit, a control unit and a propelling unit. The housing unit includes a base seat and an upper cover in liquid-tight engagement with the base seat. The control unit is disposed within the housing unit and includes a circuit module and a center-of-gravity transferring module which is electronically connected with the circuit module. The center-of-gravity transferring module has a movable weight member and a transfer driving mechanism which drives movement of the weight member so as to vary a position of a center of gravity of the underwater robotic device and to control downward and upward moving directions of the underwater robotic device in the water. The propelling unit is connected with the housing unit and is electronically connected with the control unit to produce a propelling force to move the underwater robotic device forward in the water.

Abstract: The compounds represented by Formula (I), which are peripheral alkyl and alkenyl chains extended benzene derivatives, are useful as dual autotaxin (ATX)/histone deacetylase (HD AC) inhibitors. These compounds may be included in a pharmaceutical composition along with a pharmaceutically acceptable carrier, and be used in a therapeutically effective amount for prophylaxis or treatment of various diseases and disorders.

Abstract: A method for tuning a plurality of image signal processor (ISP) parameters of a camera includes performing a first iteration. The first iteration includes extracting image features from an initial image, arranging a tuning order of the plurality of ISP parameters of the camera according to at least the plurality of ISP parameters and the image features, tuning a first set of the ISP parameters according to the tuning order to generate a first tuned set of the ISP parameters, and replacing the first set of the ISP parameters with the first tuned set of the ISP parameters in the plurality of ISP parameters to generate a plurality of updated ISP parameters.

Abstract: An embodiment phase change material switch may include a first phase change material element, a second phase change material element, a first conductor electrically connected to a first end of each of the first phase change material element and the second phase change material element such that the first conductor is configured as a first terminal of an electrical circuit having a parallel configuration, a second conductor electrically connected to a second end of each of the first phase change material element and the second phase change material element such that the second conductor is configured as a second terminal of the electrical circuit having the parallel configuration, and a heating device coupled to the first phase change material element and to the second phase change material element and configured to supply a heat pulse to the first phase change material element and to the second phase change material element.

Abstract: A semiconductor device includes a semiconductor substrate having a first source/drain region, a semiconductor layer, a first floating gate electrode, a first control gate electrode, a second floating gate electrode, a second control gate electrode, and an erase gate electrode. The semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode laterally surrounds the first semiconductor layer. The first control gate electrode laterally surrounds the first floating gate electrode and the first semiconductor layer. The second floating gate electrode laterally surrounds the first semiconductor layer. The second control gate electrode laterally surrounds the second floating gate electrode and the semiconductor layer.

Abstract: A semiconductor may include a handle substrate, a semiconductor material layer on which semiconductor devices, metal interconnect structures, dielectric material layers, and an inductor structure are located, and a patterned magnetic shielding layer including at least one portion of a ferromagnetic material having relative permeability of at least 20 and disposed between the semiconductor material layer and the handle substrate and reducing electromagnetic coupling between the inductor structure and the handle substrate.

Abstract: A device structure includes a voltage regulator circuit, which includes: a first semiconductor die including a pulse width modulation (PWM) circuit and connected to a PWM voltage output node at which a pulsed voltage output is generated; and a series connection of an inductor and a parallel connection circuit, the parallel connection circuit including a parallel connection of capacitor-switch assemblies. A first end node of the series connection is connected to the PWM voltage output node; a second end node of the series connection is connected to electrical ground; each of the capacitor-switch assemblies includes a respective series connection of a respective capacitor and a respective switch; and each switch within the capacitor-switch assemblies is located within the first semiconductor die.

Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Abstract: A substrate processing chamber is provided. The chamber includes a substrate support having an upper surface, a reflector disposed above the substrate support, the reflector includes a body comprising an upper opening having a first diameter, and a bottom opening having a second diameter different than the first diameter, a flange protruding radially from an outer circumference of the body, wherein the flange comprises a plurality of holes. The chamber also includes a plurality of heating elements disposed around the reflector. The chamber further includes a plurality of support kits, each support kit comprising a bar member, and a first fastener removably coupled to the bar member, and a cooling plate coupled to the flange by the plurality of support kits.

Abstract: A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: A flash memory controller includes a specific buffer and a processor. The specific buffer allocates a cache space. The processor receives a specific host address sent from the host device, reads and loads a corresponding address pointer mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer linker, determines a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reads and loads a corresponding address mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer corresponding to the specific host address, and finds a specific flash memory address from the corresponding address mapping table according to the specific host address to perform an access operation in response to the found specific flash memory address.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor structure, a dielectric bonding structure, a second semiconductor structure, and a through via structure. The first semiconductor structure includes a first substrate and a first back-end-of-line (BEOL) structure over the first substrate. The dielectric bonding structure is over the first semiconductor structure. The second semiconductor structure is over the dielectric bonding structure. The second semiconductor structure includes a second BEOL structure over the dielectric bonding structure and a second substrate over the second BEOL structure. The through via structure penetrates the second semiconductor structure and the dielectric bonding structure to connect the first BEOL structure and the second BEOL structure. A method for forming a semiconductor package structure is also provided.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A semiconductor die set is placed adjacent to a lower conductive via. The semiconductor die set and the lower conductive via are at least laterally encapsulated with a lower encapsulating material to form a lower encapsulated semiconductor device. A lower redistribution structure is formed over the lower encapsulated semiconductor device. A sensor die is placed adjacent to an upper conductive via, wherein the sensor die has a pad and a sensing region. The sensor die and the upper conductive via are encapsulated with an upper encapsulating material to form an upper encapsulated semiconductor device. An upper redistribution structure is formed over the upper encapsulated semiconductor device, wherein the upper redistribution structure is connected to the pad and reveals the sensing region of the sensor die.

Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.

Abstract: A resin composition includes 10 parts by weight of a first prepolymer and 5 parts by weight to 30 parts by weight of a vinyl group-containing polyphenylene ether resin, wherein the first prepolymer is prepared by subjecting a reaction mixture to a prepolymerization reaction, and the reaction mixture including a polyphenylmethane maleimide, a compound of Formula (1) and a compound of Formula (2) at a weight ratio of 100:10-30:15-45, and the resin composition is absent of a second prepolymer which is prepared by subjecting a maleimide and bis(trifluoromethyl)benzidine to a prepolymerization reaction. An article made from the resin composition may achieve improvement in at least one of the properties including ratio of electroless copper plating, storage modulus and copper foil peeling strength.

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

Abstract: A method of manufacturing an integrated circuit includes following operations. A stack of a plurality pair of first layers and second layers alternately arranged is formed over a substrate. A plurality of first holes is formed in the stack. An isolation layer is formed to cover sidewalls of the first holes. A plurality of conductive features is formed in the first holes. A plurality of second holes are formed in the stack. Each of the second holes exposes a portion of a sidewall of at least one of the conductive features. A channel layer is formed to cover sidewalls of the second holes and the portions of the sidewalls of the conductive features. The second layers of the stack are replaced with a plurality of gate layers.

Abstract: Disclosed is a system and/or apparatus for a specifically configured and/or adapted electronic device that can provide interference shielding. The disclosed system and apparatus can be embodied with various combinations of components to effectuate improved thermal resistance while reducing noise within the device and/or among components of the device. The specifically configured components of the device can have specifically configured constitutions which can effectuate the thermal and noise limiters enabled by the disclosed system/apparatus.