Patents by Inventor Hung Liu

Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114449
    Abstract: A network node may transmit a first signal to a first radio at a user equipment (UE). The UE may receive the first signal from the network node. The first signal may include a first configuration for a second radio at the UE. The UE may operate the second radio in a first mode based on the first configuration received via the first radio. The first radio may have a lower power consumption than the second radio or the second radio may have the lower power consumption than the first radio. For example, one radio may be a low-power wake-up radio (LP-WUR) having a lower power consumption than a main radio (MR) at the UE. The network node and the UE may communicate with one another via the second radio at the UE based on the first configuration transmitted to the first radio.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Ahmed ELSHAFIE, Hung Dinh LY, Huilin XU, Wanshi CHEN, Changhwan PARK, Linhai HE, Yuchul KIM, Wei YANG, Peter GAAL, Le LIU, Diana MAAMARI
  • Publication number: 20240113414
    Abstract: Disclosed is an electronic device including a device body and an antenna module. The antenna module includes a conductive element and at least one antenna element. The conductive element includes a main body portion and at least one assembly portion connected with each other. The at least one assembly portion is assembled on the device body. The at least one antenna element is disposed on the device body and coupled with the conductive element to excite a first resonance mode. The at least one assembly portion overlaps the at least one antenna element in the length direction of the main body portion.
    Type: Application
    Filed: September 24, 2023
    Publication date: April 4, 2024
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chih-Heng Lin, Li-Chun Lee, Shih-Chia Liu, Jui-Hung Lai, Hung-Yu Yeh
  • Publication number: 20240110829
    Abstract: A display device and a light detection module are provided. The display device includes a display panel and the light detection module. The light detection module is capable of detecting an optical feature of a display surface of the display panel, and includes a shaft portion, a rod portion, and a light detector. The shaft portion has a shaft extension direction. The rod portion has a rod extension direction, and takes the shaft portion as a rotation shaft. An included angle between the rod extension direction and the shaft extension direction is between 125 degrees and 145 degrees.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Applicant: CHAMP VISION DISPLAY INC.
    Inventors: Chin-Ku Liu, Chia-Hung Yu
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Publication number: 20240112842
    Abstract: An inductor and a method of forming the same are provided. The inductor includes a patterned wire structure. The patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. The conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. The dielectric film covers the outer surface. The magnetic shell covers the dielectric film. The dielectric film is between the conductive core and the magnetic shell.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng Lu, Chien-Hung Liu, Nuo Xu
  • Patent number: 11949226
    Abstract: An external power supply system for spindles is revealed. The external power supply system includes a tool holder, a rectifier circuit, an overvoltage protection circuit. and a buck/boost converter. The tool holder receives an external power source of a spindle while the rectifier circuit converts the external power source into a rectified output signal with a power factor through step-down transformation. The overvoltage protection circuit is used to check whether the rectified output signal is larger than an overvoltage signal for outputting an operating potential or a non-operating potential. The buck/boost converter is used for receiving the rectified output signal with the power factor and converting the rectified output signal to an output voltage according to the power factor. Then the output voltage is provided to a load of a low voltage power supply, a high voltage power supply, or a constant voltage power supply.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: April 2, 2024
    Assignee: NATIONAL CHUNG HSING UNIVERSITY
    Inventors: Chien-Hung Liu, Yu-Hung Li
  • Patent number: 11948895
    Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: April 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
  • Patent number: 11949609
    Abstract: Various proposed schemes pertaining to extreme high-throughput (EHT) preamble designs for transmissions to mixed clients in wireless communications are described. In one example, an aggregated Physical Layer Convergence Procedure (PLCP) protocol data unit (PPDU), which is transmitted over a plurality of 80-MHz bandwidths with data for a plurality of stations (STAs), is received. A preamble of a specific one of the plurality of 80-MHz bandwidths is then decoded.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: April 2, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Jianhan Liu, Hung-Tao Hsieh, Shengquan Hu
  • Patent number: 11950016
    Abstract: The present invention provides a control method of a receiver. The control method includes the steps of: when the receiver enters a sleep/standby mode, continually detecting an auxiliary signal from an auxiliary channel to generate a detection result; and if the detection result indicates that the auxiliary signal has a preamble or a specific pattern, generating a wake-up control signal to wake up the receiver before successfully receiving the auxiliary signal having a wake-up command.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 2, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chun-Chia Chen, Chih-Hung Pan, Chia-Chi Liu, Shun-Fang Liu, Meng-Kun Li, Chao-An Chen
  • Publication number: 20240105775
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu CHIANG, Hsiao-Han LIU, Yuan-Hung TSENG, Chih-Yung LIN
  • Publication number: 20240105644
    Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
  • Publication number: 20240107087
    Abstract: The subject application relates to a server, terminal and non-transitory computer-readable medium. The server for handling streaming data for a live streaming, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: recording the streaming data for the live streaming; storing the streaming data as archive contents with first identifier; receiving interaction information during the live streaming; storing the interaction information as contexts with second identifier, transmitting the archive contents with first identifier to a first user terminal; and transmitting the contexts to the first user terminal according to the first identifier and the second identifier. According to the subject application, the archive contents may be more immersive and the user experience may be enhanced.
    Type: Application
    Filed: June 26, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Chuan CHANG, Kun-Ze LI, Che-Wei LIU, Chieh-Min CHEN, Kuan-Hung LIU
  • Publication number: 20240104746
    Abstract: The present invention discloses a vessel tracking and monitoring system and operating method thereof. Specifically, the vessel tracking and monitoring system comprises at least one camera, a processing module and a storage module. On the other hand, the processing module may keep the water object which is detected and recognized by the at least one camera in the center area of a monitoring screen. Therefore, the present invention may track and recognize the type of the at least one water object, assisting areas such as ports in managing and tracking water object arrivals and departures under various environmental conditions.
    Type: Application
    Filed: December 15, 2022
    Publication date: March 28, 2024
    Inventors: CHIA-YU WU, YAN-SHENG SONG, YU-TING PENG, CHIEN-HUNG LIU
  • Publication number: 20240103378
    Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system including a radiation source and an EUV control system integrated with the radiation source. The EUV control system includes a 3-dimensional diagnostic module (3DDM) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3D) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an EUV control module designed to adjust the radiation source. The analysis module is coupled with the database and the EUV control module. The database is coupled with the 3DDM and the analysis module. The EUV control module is coupled with the analysis module and the radiation source.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Tai-Yu CHEN, Tzu-Jung PAN, Kuan-Hung CHEN, Sheng-Kang YU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Patent number: 11943643
    Abstract: An access point (AP) and a station (STA) communicate with each other, with the AP indicating to the STA either or both of a preamble detection (PD) channel and a signaling (SIG) content channel and with the STA being initially monitoring a primary frequency segment of a plurality of frequency segments in an operating bandwidth of the AP. A downlink (DL) or triggered uplink (UL) communication is performed between the AP and the STA during a transmission opportunity (TXOP) such that: (i) during the TXOP, the STA monitors a preamble on the PD channel and decodes a SIG content on the SIG content channel; and (ii) after an end of the TXOP, the STA switches to the primary frequency segment.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 26, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Kai Ying Lu, Yongho Seok, Hung-Tao Hsieh, Cheng-Yi Chang, James Chih-Shi Yee, Jianhan Liu, Po-Yuen Cheng
  • Patent number: 11942433
    Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
  • Publication number: 20240094498
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Wei-Jhe SHEN, Shou-Jen LIU, Kun-Shih LIN, Yi-Ho CHEN
  • Publication number: 20240096834
    Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Inventors: Shih Hsuan HSU, Chan-Chung CHENG, Chun-Chen LIU, Cheng-Hung CHEN, Peng-Ren CHEN, Wen-Hao CHENG, Jong-l MOU
  • Publication number: 20240096941
    Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 21, 2024
    Inventors: SHIH-JUNG TU, PO-WEI LIU, TSUNG-YU YANG, YUN-CHI WU, CHIEN HUNG LIU
  • Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG