Abstract: The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis.

Abstract: A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor.

Abstract: An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure.

Abstract: A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.

Abstract: A mobile electronic device includes a main body, a support frame, and a switch. When the support frame is in the first mode and used to support the main body, the main body is required to execute the first function by the support frame and the switch. For example, the first function is used to control the display and includes related functions of multimedia reproducing. In addition, when the support frame is in the second mode and used to support the main body, the main body is required to execute the second function by the support frame and the switch. For example, the second function is used to control the speaker and includes related functions. Whereby, the mobile electronic device includes different two modes to instinctively and automatically switch between video and audio files reproducing.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract: A pin out designation method for package board codesign having steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns, use the pin patterns to construct multiple pin blocks, group the pin blocks around four sides of a chip and adjusts the pin blocks into a minimized package size of the chip.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.

Abstract: In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is set as a gravity point to attract an input of the (N+1)th 2-pin logic cell, thereby optionally flipping the (N+1)th 2-pin logic cell.

Abstract: A leather decorative plate comprises a leather layer that is provided with a thermoplastic PU layer on its inner surface. The thermoplastic PU layer is bent to form a space. A method for manufacturing the leather decorative plate comprises the steps of attaching a thermoplastic PU layer to the inner surface of a leather layer, placing the two layers into a mold for proceeding with heating and pressing procedures and softening the thermoplastic PU layer to shape simultaneously the leather layer and the thermoplastic PU layer, forming a space defined by the inner surface of the thermoplastic PU layer for covering directly the surface of a 3C product. In practice, the thermoplastic layer and the leather layer can be heated in advance and then are put into the mold to be pressed to form a faceplate.

Abstract: Disclosed is a method of producing outer covering on a housing of product. A thermosetting adhesive is respectively applied to the inner surface of a flexible covering layer and the outer surface of a housing, and the thermosetting adhesive is dried after being applied thereto. The flexible covering layer and the housing are superimposed and disposed into the lower mold half of a mold, wherein the thermosetting adhesives are softened by a heat and pressure treatment during an assembling process of the lower mold half and a upper mold half, so as to adhere firmly the flexible covering layer to the housing used for consumer electronics.

Abstract: In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is set as a gravity point to attract an input of the (N+1)th 2-pin logic cell, thereby optionally flipping the (N+1)th 2-pin logic cell.

Abstract: A system for image processing in a multiview video environment including a first camera and a second camera is disclosed.

Abstract: A mobile electronic device includes a main body, a support frame, and a switch. When the support frame is in the first mode and used to support the main body, the main body is required to execute the first function by the support frame and the switch. For example, the first function is used to control the display and includes related functions of multimedia reproducing. In addition, when the support frame is in the second mode and used to support the main body, the main body is required to execute the second function by the support frame and the switch. For example, the second function is used to control the speaker and includes related functions. Whereby, the mobile electronic device includes different two modes to instinctively and automatically switch between video and audio files reproducing.

Abstract: A hand-held electronic device being held by a user with a single hand for dialing or with both hands for inputting characters includes a body, a keyboard, two sensors respectively disposed on two opposite sides of the body, and a backlight source. The keyboard has keys forming a region marked with a QWERTY keyboard and a region overlapping the above region and marked with a phone keypad. The sensors detect whether the body is held by a single hand on one side or by both hands on two sides and let the backlight source light up the region marked with the phone keypad on the keyboard when the body is held by a single hand. Thus, the region marked with the phone keypad is highlighted out of the QWERTY keyboard, so it is easy for the user to identify the key numbers and dial quickly.

Abstract: A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region adjacent the gate stack, a deep source/drain region adjoining the LDD region, and a graded silicide region on the deep source/drain region and the LDD region. The graded silicide region includes a first portion having a first thickness and a second portion adjoining the first portion and having a second thickness substantially less than the first thickness. The second portion is closer to a channel region than the first portion.

Abstract: A handheld communication device having dual operating modes includes a casing, a display and a keyboard. The casing is formed with an accommodating trough. One side of the accommodating trough is provided with a first connecting port. Further, the casing is provided thereon with a receiver. The display is sealed to cover on the accommodating trough and is displaceable with respect to the casing. The keyboard is detachably received in the accommodating trough. One side of the keyboard is provided with a second connecting port for insertion to correspond to the first connecting port. The keyboard is provided with an emitter for transmitting wireless signals to the receiver and a battery module for providing the necessary power of the emitter. Via the mutual insertion and disconnection between the second connecting port and the first connecting port, wired and wireless operating modes can be switched.

Abstract: A power-managing key apparatus uses a power key to integrate the function of ACPI management of computer hardware and hibernation on/off of operation system. A processor coupled to the power key detects pressing-time parameters of the power key and a current state of the computer. The processor sends a hardware signal to emulate ACPI power button function in order to power on/off computer and awake the computer from a power saving mode. The processor sends a software signal to an operation system of the computer to disable/enable a hibernation state. Therefore, the complicated power management performed by computer hardware and operation system can be simplified.