Abstract: A cloud data storage system is provided for multiple clients to access data of files comprising at least one node connecting to a first storage means; at least one namenode module for processing file operations issued from the clients, namenode module issuing data access instructions to access and maintain the metadata on the first storage means; at least one datanode module respectively executing on at least one node, each datanode module functioning to scan and access a second storage means connected thereto; at least one data import module selectively executing on nodes in which datanode module are executing, the data import module scanning a second storage means newly connected to the cloud data storage system and obtaining a corresponding metadata, and executing data migration operation for the data in second storage means without actual physical uploading operation.

Abstract: The invention discloses a data storage system and managing method thereof. The data storage system according to the invention includes N storage devices, a backup memory and a controller where N is a natural number. Each storage device has a respective write cache. Once the data storage system suffers from power failure, the backup memory still reserves data stored therein. The controller receives data transmitted from an application I/O request unit, executes a predetermined operation for the received data to generate data to be written, transmits the data to be written to the write caches of the storage devices, duplicates the data to be written into the backup memory, and labels the duplicated data in the backup memory as being valid in response to a writing confirm message sent from the storage devices.

Abstract: Aspects of a method and system for processing signals in a high performance receive chain may include amplifying a plurality of radio frequency signals in one or more respective one or ones of a plurality of amplifier chains in a multistandard radio frequency front-end, which may comprise one or more shared processing stages. The plurality of radio frequency signals may be compliant with a plurality of radio frequency communication standards and may be received concurrently. The one or more shared processing stages may be shared between two or more of the plurality of amplifier chains. Each of the two or more of the plurality of amplifier chains may be operable to amplify signals compliant with different radio frequency communication standards.

Abstract: An RF receiver and an RF transmitter, which are integrated in a single substrate, are operable to share a single reconfigurable filter to perform RF receiver filtering and RF transmitter filtering. The reconfigurable filter is configured to operate as a bandpass filter such as an image rejection bandpass filter for receiving RF signals by the RF receiver. The reconfigurable filter operates as a low pass filter for transmitting RF signals by the RF transmitter. The reconfigurable filter is configured to operate in a RF receiver filtering mode or a RF transmitter filtering mode, respectively. The reconfigurable filter is enabled to share configurable circuit components of the radio transceiver in both the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode. The reconfigurable filter transitions between the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode via reconfiguring the shared configurable circuit components.

Abstract: The invention discloses a data storage system and a control method thereof. The data storage system according to the invention includes N groups of storage devices, where N is an integer larger than 1. The invention is to judge if the use information of one of the batches of data satisfies the set of condition thresholds relative to the group of storage devices where said one batch of data is stored, and if NO, to re-allocate said one batch of data to one of the group of storage devices whose condition thresholds are satisfied by the use information of said one batch of data and to update the virtual drive locations of said one batch of data mapping the logical locations of the storage devices.

Abstract: The invention discloses a network-attached storage system including an interface module, a plurality of storage devices and a storage module. The interface module is configured to be attached to a network. The interface module is for receiving a transmission protocol information transmitted over the network, and processing the information into storage data and access instructions. The storage module is for receiving the storage data and the access instructions, and controlling, according to the access instructions, access of the storage data to the primary storage devices through a transmission interface.

Abstract: An alternate adjacent channel interference (AACI) filter is integrated into an intermediate frequency (IF) channel select filter to filter received RF signals. The IF channel select filter is an IF staged structure comprising successive IF stages. Each of the successive IF stages is a 2-biquad integrator. The AACI filter is integrated into the first IF stage of the IF channel select filter by re-using circuit components such as an operational amplifier, an input resistor, and a shunt capacitor of the first IF stage. The shunt capacitor is coupled between a middle point of the input resistor and ground. The AACI filter is realized via different equivalent implementations of the re-used circuit components of the first IF stage. A value of the shunt capacitor of the AACI filter becomes a fixed-value when a value the input resistor is inversely proportional to the bandwidth of the AACI filter.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second standard. The transmitter comprises an oscillator, a frequency divider, a mixer, and a filter. The oscillator is configured to output a first frequency that is outside of a frequency harmonic of the frequency generator. The frequency divider is coupled to the oscillator and divides the first frequency by a selective divide ratio to produce a second frequency. The mixer is configured to receive the first and second frequencies, which combines them to produce a mixed frequency. The filter is then used to filters the mixed frequency to obtain the higher portion of the mixed frequency. The divide ratio of the frequency divider is selected base on the desired output frequency of the transmitter such that a 2.4 GHz or 5 GHz ISM band frequency is achieved.

Abstract: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.

Abstract: The invention discloses a data storage system and a control method thereof. The data storage system according to the invention includes N groups of storage devices, where N is an integer larger than 1. The invention is to judge if the use information of one of the batches of data satisfies the set of condition thresholds relative to the group of storage devices where said one batch of data is stored, and if NO, to re-allocate said one batch of data to one of the group of storage devices whose condition thresholds are satisfied by the use information of said one batch of data and to update the virtual drive locations of said one batch of data mapping the logical locations of the storage devices.

Abstract: A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second standard. The transmitter comprises an oscillator, a frequency divider, a mixer, and a filter. The oscillator is configured to output a first frequency that is outside of a frequency harmonic of the frequency generator. The frequency divider is coupled to the oscillator and divides the first frequency by a selective divide ratio to produce a second frequency. The mixer is configured to receive the first and second frequencies, which combines them to produce a mixed frequency. The filter is then used to filters the mixed frequency to obtain the higher portion of the mixed frequency. The divide ratio of the frequency divider is selected base on the desired output frequency of the transmitter such that a 2.4 GHz or 5 GHz ISM band frequency is achieved.

Abstract: The invention discloses a data storage system and a synchronizing method for consistency thereof, especially for the data storage system specified in RAID 5 architecture. The data storage system according to the invention includes N storage devices, where N is an integer equal to or larger than 3. The synchronizing method according to the invention performs writing commands for the designated storage device among the N storage devices, and reading commands for the other (N?1) storage devices, to reduce synchronization time of the data storage system.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.

Abstract: Aspects of a method and system for processing signals in a high performance receive chain may include amplifying a plurality of radio frequency signals in one or more respective one or ones of a plurality of amplifier chains in a multistandard radio frequency front-end, which may comprise one or more shared processing stages. The plurality of radio frequency signals may be compliant with a plurality of radio frequency communication standards and may be received concurrently. The one or more shared processing stages may be shared between two or more of the plurality of amplifier chains. Each of the two or more of the plurality of amplifier chains may be operable to amplify signals compliant with different radio frequency communication standards.