Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

Abstract: Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A second impulse signal may be generated utilizing an input divided signal. A programmable delay signal may be generated based on the generated first impulse signal and the generated second impulse signal. The generation of the first impulse signal and the generation of the second impulse signal may be controlled via the generated programmable delay signal. The generated first impulse signal and the generated second impulse signal may be delayed utilizing a programmable delay. The delayed first impulse signal and the delayed second impulse signal may be ANDed to generate the programmable delay signal, and the generated programmable delay signal may comprise a reset signal.

Abstract: A low phase noise crystal oscillator with supply noise filtering is provided and may comprise receiving an input voltage at a positive potential input of an oscillator circuit, which may comprise an oscillator core and a buffer coupled to an output of the oscillator core. Noise caused by the input voltage that may affect the buffer may be filtered using a resistor coupled between the positive potential input of the oscillator circuit and the input voltage, and a capacitor coupled between the positive potential input of the oscillator circuit and a ground of the oscillator circuit. The noise may be filtered via a low pass filter, which may comprise at least the resistor and the capacitor. A cutoff frequency may be selected for the low pass filter, and a resistance value for the resistor and a capacitance value for the capacitor may be selected appropriately.

Abstract: A method and apparatus for fractional-N synthesis includes processing that begins by generating a 1st feedback frequency from the output frequency based on a fixed divider value. The processing continues by generating a 2nd feedback frequency from the output frequency based on a selectable divider value, a modified fractional value of the divider value, and a modified integer value of the divider value. The processing continues by determining whether the fractional value of the divider value is within a range of fractional values. If so, the 1st feedback frequency is used to produce the output. If the fractional portion of the divider value is not within the range of fractional values, the 2nd feedback frequency is used to produce the output frequency.

Abstract: A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second standard. The transmitter comprises an oscillator, a frequency divider, a mixer, and a filter. The oscillator is configured to output a first frequency that is outside of a frequency harmonic of the frequency generator. The frequency divider is coupled to the oscillator and divides the first frequency by a selective divide ratio to produce a second frequency. The mixer is configured to receive the first and second frequencies, which combines them to produce a mixed frequency. The filter is then used to filters the mixed frequency to obtain the higher portion of the mixed frequency. The divide ratio of the frequency divider is selected base on the desired output frequency of the transmitter such that a 2.4 GHz or 5 GHz ISM band frequency is achieved.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: A method and system for VCO with switchable varactor for low KVCO variation is provided. Aspects of a method for controlling a signal may comprise controlling an oscillating frequency of a time varying signal in a circuit, and controlling a change in the oscillating frequency based on switching of a plurality of varactors. The switching of the varactors may control a change in the oscillating frequency based on a control voltage. The method may further comprise minimizing a change in the rate of change in the oscillating frequency based on the switching of the varactors. Aspects of a system for controlling a signal may comprise circuitry that controls an oscillating frequency of a time varying signal in a circuit, and circuitry that controls a change in the oscillating frequency based on switching of a plurality of varactors. An executable computer program may cause a machine to execute steps as described above.

Abstract: A charge pump provides charge based on a phase difference between a reference signal and a feedback signal. The relationship between the charge and the phase difference is referred to as the charge phase relationship. Charge pumps typically have a non-linear charge phase relationship. A non-linear portion of the charge phase relationship occurs about a point at which the charge and the phase difference are substantially zero. Points along charge phase relationship that represent the performance of charge pump are referred to as the charge phase characteristic of the charge pump. The charge pump includes an offset current circuit, which biases the charge pump to have a linear charge phase characteristic. For example, the charge pump is biased to have a charge phase characteristic that does not overlap with the non-linear portion of the charge phase relationship.

Abstract: An oscillator that provides a quadrature output and has a cross-coupled configuration is disclosed. The oscillator generates an output signal having a frequency. Two phase shift circuits, or stages, are activated by a control signal to provide phase shifts within the oscillator. Each phase shift circuit includes poles to provide the phase shift. A pole includes a varactor to tune, adjust or vary the phase shift accordingly.

Abstract: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.

Abstract: A multi-modulus divider for high speed applications is provided and may comprise a multistage divider generating a divided signal from an output portion of a divider module for a current stage. The divided signal may be fed back to an input portion of the divider module in the current stage via a reduced feedback delay path. If the input portion of the divider module in the current stage is coupled to the divider module in a previous stage, a first load signal may be communicated from the divider module in the current stage to the divider module in the previous stage. If the divider module in the current stage is coupled to the divider module in the previous stage, the method may further comprise receiving the divided signal from the divider module in the previous stage.

Abstract: A data storage system including an array of storage devices and a storage controller is provided. The array of storage devices is configured to store information in the form of a plurality of stripes. The storage controller is configured to write a plurality of code words forming each stripe to the array of storage devices. Each code word comprises a plurality of data blocks and at least one redundancy block. A redundancy check matrix is previously provided and one subset including any k columns of elements in the redundancy check matrix is invertible. The storage controller generates the redundancy block according to the plurality of data blocks and the redundancy check matrix. Once up to k storage devices among the array of storage devices are failed, the other un-failed storage devices and the redundancy check matrix are utilized to recover the failed storage devices.

Abstract: A method for managing a data storage system is provided. The data storage system includes a primary storage device and a spare storage device. The primary storage device includes a plurality of sections. The method first judges whether the primary storage device conforms to a first standard. Once the judging result is NO, the primary storage device is replaced with the spare storage device. The method then scans the primary storage device, checks which sections are failed in the primary storage device, and locates the failed sections. Then, the method repairs the failed sections that can be repaired and judges whether the primary storage device conforms to a second standard. If the primary storage device conforms to the second standard, the method sets the primary storage device as a new spare storage device.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An redundant array of independent disks (RAID) storage device is provided. The RAID comprises M number of storage devices, and the storage blocks of the same J-column in each storage device comprises complete stripe blocks and at least a plurality of partially complete stripe blocks. Inside the same stripe block, the total number of the storage blocks (L) is smaller than the number of the storage device (M), and the quantity of the storage blocks (M) is not multiple of storage blocks (L).

Abstract: A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module. The detection module is operably coupled to produce a difference signal based on a difference between a reference oscillation and a feedback oscillation. The control conversion module is operably coupled to convert the difference signal into a control signal. The controlled oscillation module is operably coupled to produce an output oscillation based on the control signal. The divider module is operably coupled to produce the feedback oscillation based on the output oscillation. The power distribution module is operably coupled to receive a supply voltage and to provide an individual supply voltage to at least one of the detection module, the control conversion module, the controlled oscillation module, and the divider module to optimize at least one of performance and power consumption of the phase locked loop.

Abstract: Methods and systems for calibrating a frequency of a circuit are disclosed herein and may comprise dividing a feedback frequency of an output frequency signal to generate a divided frequency signal. Open loop calibration may be performed based on a binary search of the generated divided frequency signal to generate a coarse calibrated frequency signal. Subsequently, a closed loop calibration may be performed on the coarse calibrated frequency signal to generate a fine calibrated frequency signal. A binary code may be generated utilizing the binary search of the generated divided frequency signal. Capacitance within the circuit may be adjusted based on the generated binary code. A control voltage for the circuit may be measured by closing a phase locked loop (PLL) with the circuit. If the measured control voltage is not within a determined voltage range, a calibration flag signal may be generated.

Abstract: Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A second impulse signal may be generated utilizing an input divided signal. A programmable delay signal may be generated based on the generated first impulse signal and the generated second impulse signal. The generation of the first impulse signal and the generation of the second impulse signal may be controlled via the generated programmable delay signal. The generated first impulse signal and the generated second impulse signal may be delayed utilizing a programmable delay. The delayed first impulse signal and the delayed second impulse signal may be ANDed to generate the programmable delay signal, and the generated programmable delay signal may comprise a reset signal.