Patents by Inventor Hung Wang

Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250019941
    Abstract: The water supply system utilizes a water flow rate sensor to monitor the water flow status of a sensor faucet and analyze whether any malfunction is present. In the event of a malfunction, the system utilizes a telecommunications network to transmit the fault message, enabling management personnel to identify the specific sensor faucet that is faulty, determine the cause of the malfunction, and contact maintenance personnel for repairs in the water supply system.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 16, 2025
    Inventor: Hsiang-Hung Wang
  • Patent number: 12198979
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Publication number: 20250014594
    Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.
    Type: Application
    Filed: September 19, 2024
    Publication date: January 9, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming MAO, Yung-Hung WANG, Chih-Ching HU, Chen-Jung CHIEN, Carlos CORONA, Hongping YUAN, Ming JIANG, Goncalo Marcos BAIÃO DE ALBUQUERQUE
  • Publication number: 20250007389
    Abstract: A circulating current suppression method of a power system having a plurality of power modules is provided. Each power module includes a high-voltage bus, a low-voltage bus and a balance circuit having a neutral voltage. The circulating current suppression method includes: in each balance circuit, disposing a first capacitor electrically coupled between the high-voltage bus and the neutral voltage, and disposing a second capacitor electrically coupled between the neutral voltage and the low-voltage bus; acquiring a current effective value of an input of each power module; if detecting that the current effective value of at least one power module doesn't remain at a current reference value, determining that a circulating current occurs in the at least one power module; and operating the balance circuit of the at least one power module to charge the first capacitor or the second capacitor to regulate the neutral voltage for suppressing the circulating current.
    Type: Application
    Filed: September 7, 2023
    Publication date: January 2, 2025
    Inventors: Hsin-Chih Chen, Li-Hung Wang, Chao-Li Kao, Yi-Ping Hsieh, Hung-Chieh Lin
  • Patent number: 12181949
    Abstract: A power management device and a management method thereof are provided. The power management device includes a switch, a detection circuit and a controller. The switch receives an external power. The detection circuit receives an internal power and at least one operation power. The detection circuit determines whether at least one of the internal power and the operation power is in a preset specification range or not to generate a protection activate signal. The controller sets a protection flag according to the protection activate signal, and generates a control signal according to the protection flag by executing an application program. The controller transmits the control signal to turn off the switch.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: December 31, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Tsang-Ming Chang, Yi-Hsun Lin, Ching-Ji Liang, Hsun-Hung Wang, Hao-Jung Chiou
  • Patent number: 12175030
    Abstract: A pen mouse is provided for controlling a movement of a cursor displayed on a monitor. The pen mouse includes a pen and an optical detection module assembled in the pen. The optical detection module includes a circuit board, two sensors, and a laser emitter, the latter two of which are assembled onto the circuit board. When the pen mouse is moved along a working surface to implement a mouse control motion, the two sensors receive a detection light emitted from the laser emitter and reflected by the working surface, so as to determine whether the mouse control motion is a pen-tilted motion or a pen-spinning motion, thereby compensating the movement of the cursor.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: December 24, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Yen-Hung Wang, Hung-Yu Lai
  • Publication number: 20240416556
    Abstract: A slurry sprayer for supplying a slurry to a wire saw during ingot slicing is disclosed. The slurry sprayer includes a main body and a cover plate that is detachable from the main body for cleaning the slurry sprayer. In some embodiments, the slurry sprayer includes an adjustable support that allows the incline angle of the sprayer to be adjusted and allows the vertical and horizontal position of the slurry sprayer to be adjusted. In some embodiments, the slurry sprayer includes two feed openings to allow the slurry pressure to be more equalized across the slurry sprayer.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Inventors: Chia Ming Liu, Chien Ming Chen, Jui Hung Wang, Hao Chen
  • Publication number: 20240419383
    Abstract: Disclosed are an image generating device and a communication circuit thereof. The communication circuit includes a first pull-up resistor, an unidirectional current component, a signal isolation component and a signal switch. The first pull-up resistor receives a standby voltage. The unidirectional current component is coupled between the first pull-up resistor and a (CEC) pin. The signal isolation component is coupled to a path between the pin CEC and the signal switch, where a first end of the signal isolation component is controlled by the standby voltage. The signal switch is coupled to a second end of the signal isolation component, and the signal switch couples the second end of the signal isolation component to a second pull-up resistor of a processor or the signal switch couples the second end of the signal isolation component to a third pull-up resistor of a port according to a system voltage.
    Type: Application
    Filed: June 12, 2024
    Publication date: December 19, 2024
    Applicant: Coretronic Corporation
    Inventors: Nien-Hung Wang, Jeng-An Liao
  • Patent number: 12164118
    Abstract: There is provided a lens including a first curved surface and a second curved surface. The first curved surface and the second curved surface have different focal distances and are arranged interlacedly along a radial direction of the lens.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: December 10, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Hui-Hsuan Chen, Yen-Hung Wang, Wen-Yen Su
  • Publication number: 20240404552
    Abstract: A two-dimensional magnetic recording (TDMR) read head includes a lower reader and an upper reader. Each of the lower reader and the upper reader may have a dual free layer (DFL) magnetic tunnel junction structure having first and second free layers located between lower and upper shields. A synthetic antiferromagnetic (SAF) structure is located on a side of each magnetic tunnel junction. A sidewall insulating layer is located between the lower soft bias layer of the SAF structure and the first free layer. The sidewall insulating layer can have a reduced height such that an upper soft bias layer of the SAF structure is in direct contact with a sidewall of the second free layer, or the upper portion of the sidewall insulating layer located between the upper soft bias layer of the SAF structure and the sidewall of the second free layer has a reduced thickness.
    Type: Application
    Filed: August 14, 2023
    Publication date: December 5, 2024
    Inventors: Chih-Ching Hu, Yung-Hung Wang, Ming Mao, Ming Jiang, Yukimasa Okada, Goncalo Baiao de Albuquerque
  • Patent number: 12159830
    Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
  • Publication number: 20240395784
    Abstract: The present disclosure provides an electronic device. The electronic device includes a flexible carrier, an electronic component disposed over the flexible carrier, and a first flexible connection element configured to connect the flexible carrier and the electronic component. The first flexible connection element is configured to extend along a deformation direction of the electronic device. An interconnection structure is also provided.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuei-Hao TSENG, Kai Hung WANG, Chih Lung LIN
  • Publication number: 20240387252
    Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
  • Publication number: 20240385610
    Abstract: A computing system includes one or more electronic components, a first programmable device, and a baseboard management controller (BMC). The first programmable device is communicatively coupled to a first subset of the one or more electronic components. The first programmable device is configured to detect event activities associated with the first subset and to store the event activities as stored first event data. The BMC includes a system event log. The BMC is communicatively coupled to the first programmable device. The BMC is configured to receive the stored first event data and to write the stored first event data in the system event log.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: Le-Sheng CHOU, Sz-Chin SHIH, Shuen-Hung WANG, Hsien-Chang LI
  • Publication number: 20240387268
    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • Publication number: 20240387253
    Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Ren Wang, Jen Hung Wang, Tze-Liang Lee
  • Publication number: 20240381447
    Abstract: The application discloses a mobile communication device and method. The mobile communication method includes: when a collision between third party communication by a third party module and Wi-Fi communication by a Wi-Fi module is detected, determining a next Wi-Fi receiving gain; and adjusting a Wi-Fi receiving gain based on the calculated next Wi-Fi receiving gain to concurrently receive Wi-Fi signals and third party signals.
    Type: Application
    Filed: May 7, 2024
    Publication date: November 14, 2024
    Inventors: Po-Wen HSIAO, Chin-Hung WANG, Kuo-Ming CHEN
  • Publication number: 20240379152
    Abstract: A signal quality optimization system and a signal quality optimization method are provided.
    Type: Application
    Filed: September 15, 2023
    Publication date: November 14, 2024
    Inventors: MING-SHENG PENG, TING-YING WU, SHIH-HUNG WANG, WEI-ZHI CHEN
  • Publication number: 20240379541
    Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
  • Publication number: 20240369421
    Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Zi-Ang Su, Ming-Shuan Li, Shu-Hua Wu, Chih Chieh Yeh, Chih-Hung Wang, Wen-Hsing Hsieh