Patents by Inventor Hung-Wen Hsu

Hung-Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11315972
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 11246235
    Abstract: A waterproof structure includes a housing and a waterproof button. The housing has a first surface, a first side surface, and a second surface. The first side surface is recessed in the first surface to define a first opening, the first side surface is connected between the first surface and the second surface, and the second surface is exposed from the first opening. The waterproof button is disposed in the first opening and includes at least one first water blocking structure, and the first water blocking structure is pressed and deformed to abut against the first side surface.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: February 8, 2022
    Inventors: Hung-Wen Hsu, Che-Cheng Chang, Jian-Lun Chen
  • Publication number: 20210376053
    Abstract: The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Hung-Wen Hsu, Po-Han Huang, Wei-Li Huang
  • Patent number: 11139239
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
  • Publication number: 20210233945
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Publication number: 20210212230
    Abstract: A waterproof structure includes a housing and a waterproof button. The housing has a first surface, a first side surface, and a second surface. The first side surface is recessed in the first surface to define a first opening, the first side surface is connected between the first surface and the second surface, and the second surface is exposed from the first opening. The waterproof button is disposed in the first opening and includes at least one first water blocking structure, and the first water blocking structure is pressed and deformed to abut against the first side surface.
    Type: Application
    Filed: November 6, 2020
    Publication date: July 8, 2021
    Inventors: Hung-Wen HSU, Che-Cheng CHANG, Jian-Lun CHEN
  • Publication number: 20210098371
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Kai Tzeng, Wei-Li Huang
  • Publication number: 20210066357
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Inventors: Hung-Wen Hsu, Jieh-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Publication number: 20200388647
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10847560
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 10840287
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10804315
    Abstract: The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Publication number: 20200091223
    Abstract: The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10510799
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate and an image sensing element disposed within the substrate. The substrate has sidewalls defining a plurality of protrusions over the image sensing element. A first one of the plurality of protrusions including a first sidewall having a first segment. A line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Publication number: 20190363126
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 28, 2019
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20190288027
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate and an image sensing element disposed within the substrate. The substrate has sidewalls defining a plurality of protrusions over the image sensing element. A first one of the plurality of protrusions including a first sidewall having a first segment. A line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 19, 2019
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10395974
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate at low cost and with low total thickness variation (TTV). In some embodiments, an etch stop layer is epitaxially formed on a sacrificial substrate. A device layer is epitaxially formed on the etch stop layer and has a different crystalline lattice than the etch stop layer. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates. The sacrificial substrate is removed. An etch is performed into the etch stop layer to remove the etch stop layer. The etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Pei Chou, Hung-Wen Hsu, Jiech-Fun Lu, Yu-Hung Cheng, Yung-Lung Lin, Min-Ying Tsai
  • Publication number: 20190252423
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 15, 2019
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 10361234
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10304898
    Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device includes an image sensing element disposed within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element. The plurality of protrusions respectively include a sidewall having a first segment oriented at a first angle and a second segment over the first segment. The second segment is oriented at a second angle that is larger than the first angle. One or more absorption enhancement layers are arranged over and between the plurality of protrusions. The first angle and the second angle are acute angles measured through the substrate with respect to a horizontal plane that is parallel to a second side of the substrate opposite the first side.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou