Patents by Inventor Hung-Wen Hsu

Hung-Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269843
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Publication number: 20190103437
    Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device includes an image sensing element disposed within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element. The plurality of protrusions respectively include a sidewall having a first segment oriented at a first angle and a second segment over the first segment. The second segment is oriented at a second angle that is larger than the first angle. One or more absorption enhancement layers are arranged over and between the plurality of protrusions. The first angle and the second angle are acute angles measured through the substrate with respect to a horizontal plane that is parallel to a second side of the substrate opposite the first side.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 4, 2019
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10170536
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Wen Hsu, Yen-Shuo Su, Jiech-Fun Lu, Kuan Chih Huang, Tze Yun Chou, Chun-Mao Chiu, Tao-Sheng Chang
  • Patent number: 10164156
    Abstract: Structures and formation methods of an image sensor structure are provided. The image sensor structure is provided. The image sensor structure includes a substrate, a photodiode component in the substrate, and a grid structure over the substrate. The grid structure includes a bottom dielectric element over the substrate, a reflective element over the bottom dielectric element, and an upper dielectric element over the reflective element. The reflective element has a sidewall which is anti-corrosive in a basic condition and an acidic condition. The image sensor structure also includes a color filter element over the substrate and surrounded by the grid structure. The color filter element is aligned with the photodiode component.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Wei-Chuang Wu, Wei-Lin Chen, Jiech-Fun Lu
  • Patent number: 10163974
    Abstract: In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10163972
    Abstract: A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Wen Hsu, Jung-I Lin, Ching-Chung Su, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20180366536
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; a magnetic layer in the second passivation layer; and an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide. A method for manufacturing a semiconductor structure is also disclosed.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: HUNG-WEN HSU, YEN-SHUO SU, JIECH-FUN LU, KUAN CHIH HUANG, TZE YUN CHOU, CHUN-MAO CHIU, TAO-SHENG CHANG
  • Publication number: 20180337211
    Abstract: In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Publication number: 20180286907
    Abstract: Structures and formation methods of an image sensor structure are provided. The image sensor structure is provided. The image sensor structure includes a substrate, a photodiode component in the substrate, and a grid structure over the substrate. The grid structure includes a bottom dielectric element over the substrate, a reflective element over the bottom dielectric element, and an upper dielectric element over the reflective element. The reflective element has a sidewall which is anti-corrosive in a basic condition and an acidic condition. The image sensor structure also includes a color filter element over the substrate and surrounded by the grid structure. The color filter element is aligned with the photodiode component.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung SU, Hung-Wen HSU, Wei-Chuang WU, Wei-Lin CHEN, Jiech-Fun LU
  • Patent number: 10084056
    Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Hsu, Hung-Ling Shih, Jiech-Fun Lu
  • Publication number: 20180269299
    Abstract: A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Hung-Wen Hsu, Hung-Ling Shih, Jiech-Fun Lu
  • Publication number: 20180226449
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20180197903
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 12, 2018
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Patent number: 9991303
    Abstract: An image sensor structure is provided. The image sensor device structure includes a substrate, and the substrate includes an array region and a peripheral region. The image sensor device structure includes an anti-reflection layer formed on the substrate and a buffer layer formed on the anti-reflection layer. The image sensor device structure includes a first etch stop layer formed on the buffer layer and a metal grid structure formed on the first etch stop layer. The image sensor device structure also includes a dielectric layer formed on the metal grid structure.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Hsu, Ching-Chung Su, Cheng-Hsien Chou, Jiech-Fun Lu, Shih-Pei Chou, Yeur-Luen Tu
  • Patent number: 9941320
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9917121
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Publication number: 20170278881
    Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
  • Publication number: 20160276386
    Abstract: An image sensor structure is provided. The image sensor device structure includes a substrate, and the substrate includes an array region and a peripheral region. The image sensor device structure includes an anti-reflection layer formed on the substrate and a buffer layer formed on the anti-reflection layer. The image sensor device structure includes a first etch stop layer formed on the buffer layer and a metal grid structure formed on the first etch stop layer. The image sensor device structure also includes a dielectric layer formed on the metal grid structure.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen HSU, Ching-Chung SU, Cheng-Hsien CHOU, Jiech-Fun LU, Shih-Pei CHOU, Yeur-Luen TU
  • Publication number: 20160233266
    Abstract: A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.
    Type: Application
    Filed: April 6, 2016
    Publication date: August 11, 2016
    Inventors: HUNG-WEN HSU, JUNG-I LIN, CHING-CHUNG SU, JIECH-FUN LU, YEUR-LUEN TU, CHIA-SHIUNG TSAI
  • Publication number: 20160204154
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai