Patents by Inventor Hung-Wen Su

Hung-Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060172529
    Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.
    Type: Application
    Filed: February 1, 2005
    Publication date: August 3, 2006
    Inventors: Chien-Hsueh Shih, Hung-Wen Su, Minghsing Tsai
  • Publication number: 20060138668
    Abstract: A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.
    Type: Application
    Filed: December 27, 2004
    Publication date: June 29, 2006
    Inventors: Hung-Wen Su, Chien-Hsueh Shih, Minghsing Tsai, Shau-Lin Shue, Chen-Hua Yu
  • Publication number: 20060118962
    Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Jui Huang, Minghsing Tsai, Shau-Lin Shue, Hung-Wen Su, Ting-Chu Ko
  • Publication number: 20050245072
    Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Inventors: Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ming-Hsing Tsai, Hung-Wen Su, Shih-Wei Chou, Shau-Lin Shue, Kuo-Wei Cheng, Ting-Chu Ko
  • Publication number: 20050224359
    Abstract: Apparatus and method for metal electroplating. The apparatus for metal electroplating includes an electroplating tank for containing an electrolyte at a first temperature, a substrate holder for holding a semiconductor substrate, and a heater for heating the portion of the electrolyte adjacent to the substrate holder to a second temperature higher than the first temperature.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 13, 2005
    Inventors: Hung-Wen Su, Chien-Hsueh Shih, Ming-Hsing Tsai
  • Publication number: 20050211379
    Abstract: Apparatus and method for removing copper from wafer edge. The apparatus of the invention includes a bath tank for containing a chemical bath, a rotatable wafer chuck for holding a wafer vertical to the chemical bath, wherein at least the edge of the wafer is covered with a metal layer, and a sliding element is disposed on one end of the rotatable wafer chuck such that the rotatable wafer chuck can move in a vertical direction to the chemical bath.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 29, 2005
    Inventors: Hung-Wen Su, Ming-Hsing Tsai
  • Publication number: 20050097769
    Abstract: A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.
    Type: Application
    Filed: September 24, 2003
    Publication date: May 12, 2005
    Inventors: Jing-Cheng Lin, Shing-Chyang Pan, Hsien-Ming Lee, Hung-Wen Su, Shih-Wei Chou, Ming-Hsing Tsai, Shau-Lin Shue
  • Publication number: 20040214441
    Abstract: An improvement in a copper damascene process is disclosed. The improvement comprises the step of projecting an electron beam on to a chemical mechanically polished material surface having copper filled etched trenches at a known angle of incidence with respect to the material surface for a known period of time, the electron beam having a beamwidth substantially covering the material surface and a known intensity.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Inventors: Han-Hsin Kuo, Hung-Wen Su, Wen-Chih Chiou, Tsu Shih, Hsien-Ming Lee
  • Publication number: 20040188850
    Abstract: A copper filled semiconductor feature and method of forming the same having improved bulk properties the method including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Ming Lee, Hung-Wen Su
  • Patent number: 6797144
    Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: September 28, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hung-Wen Su, Shih-Wei Chou, Ching-Hua Hsieh, Shau-Lin Shue
  • Publication number: 20030209444
    Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen Su, Shih-Wei Chou, Ching-Hua Hsieh, Shau-Lin Shue