Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract: A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.

Abstract: One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure.

Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.

Abstract: Presented herein is a method of processing a device, comprising providing an electroplating bath having a leveler, the leveler having a total nitrogen-to-total carbon (TN/TOC) ratio of about 15% or less, bringing a substrate into contact with the electroplating bath, the substrate having a recess formed therein and electroplating the substrate to create a feature substantially free of voids in the substrate recess. Electroplating the substrate is performed for a time period about as long as an electrical response peak of the leveler, and optionally for at least 30 seconds. The leveler may optionally have at least one ingredient free of nitrogen and having a leveling functionality. One ingredient may be a benzene ring free of nitrogen. The leveler TN/TOC ratio is between about 3% and about 15%.

Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.

Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.

Abstract: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.

Abstract: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.

Abstract: The mechanisms of forming an interconnect structures described above involves using a reflowed conductive layer. The reflowed conductive layer is thicker in smaller openings than in wider openings. The mechanisms may further involve forming a metal cap layer over the reflow conductive layer, in some embodiments. The interconnect structures formed by the mechanisms described have better electrical and reliability performance.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract: The present invention relates to polyimide-titania hybrid thin film, which possesses relatively good surface planarization, excellent thermal properties (400<Td<550° C.), tunable refractive index (1.571<n<1.993), and highly optical transparency in the visible range. The present invention also relates to a method for preparing the polyimide-titania hybrid materials, which comprises producing a polyimide containing pendent and/or terminal carboxylic acid, coordinating the carboxylic acid with titanium of titanium alkoxide and sol-gel reacting of titanium alkoxide, to enhance the interaction between polyimide and titania and produce the polyimide-titania hybrid materials without macrophase separation. The present polyimide-titania hybrid materials are useful to produce the thin film having the above features.

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

Abstract: Methods and apparatuses for electrochemically depositing a metal layer onto a substrate. An electrochemical deposition apparatus comprises a substrate holder assembly including a substrate chuck and a relatively soft cathode contact ring. The cathode contact ring comprises an inner portion and an outer portion, wherein the inner portion directly contacts the substrate. An anode is disposed in an electrolyte container. A power supply connects the substrate holder assembly and the anode.

Abstract: A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.

Abstract: The present invention relates to polyimide-titania hybrid thin film, which possesses relatively good surface planarization, excellent thermal properties (400<Td<550° C.), tunable refractive index (1.571<n<1.993), and highly optical transparency in the visible range. The present invention also relates to a method for preparing the polyimide-titania hybrid materials, which comprises producing a polyimide containing pendent and/or terminal carboxylic acid, coordinating the carboxylic acid with titanium of titanium alkoxide and sol-gel reacting of titanium alkoxide, to enhance the interaction between polyimide and titania and produce the polyimide-titania hybrid materials without macrophase separation. The present polyimide-titania hybrid materials are useful to produce the thin film having the above features.

Abstract: An electroless plating method and the apparatus for performing the same are provided. The method includes providing a plating solution; contacting a front surface of the wafer with the plating solution; and incurring a plating reaction substantially simultaneously on an entirety of the front surface of the wafer. The step of incurring a plating reaction substantially simultaneously includes lift-dispense electroless plating and face-down immersion.

Abstract: Apparatus and method for metal electroplating. The apparatus for metal electroplating includes an electroplating tank for containing an electrolyte at a first temperature, a substrate holder for holding a semiconductor substrate, and a heater for heating the portion of the electrolyte adjacent to the substrate holder to a second temperature higher than the first temperature.