Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

Abstract: A method for plating includes positioning a substrate facing a plating solution. The method also includes immersing the substrate into the plating solution while plating a layer of material over a surface of the substrate, wherein an immersion speed of the substrate is about 100 millimeters per second (mm/s) or more while at least one portion of the substrate contacts the plating solution.

Abstract: A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

Abstract: Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

Abstract: A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract: Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

Abstract: Copper interconnect structures for interconnection. The interconnect structure has a copper recess in a damascene structure with copper filled in a via/trench of a dielectric layer. Furthermore, the interconnect structure can also have a metal cap filled the copper recess.

Abstract: Described are methods of and compositions for electrodepositing copper or other metals onto interconnects of a semiconductor substrate from an electroplating composition containing at least one nitrogen-containing additive. The nitrogen-containing additive has a molecular weight of between 10 and 1000, a concentration of between 5.0 and 10.0 milligrams per liter of the electroplating composition. The methods and compositions result in electroplated copper interconnects that have smooth surfaces that are relatively free of pits and humps.

Abstract: A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

Abstract: Electroplating composition and method. In one embodiment, the composition comprises an electrolyte solution and an amine-based copolymer comprising monomer units of ethylene oxide and propylene oxide, with the propylene oxide present in a quantity of at least about 70 wt %. The method comprises electroplating a metal onto a substrate from the electroplating composition of the invention.

Abstract: A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.

Abstract: A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

Abstract: Methods and apparatuses for electrochemically depositing a metal layer onto a substrate. An electrochemical deposition apparatus comprises a substrate holder assembly including a substrate chuck and a relatively soft cathode contact ring. The cathode contact ring comprises an inner portion and an outer portion, wherein the inner portion directly contacts the substrate. An anode is disposed in an electrolyte container. A power supply connects the substrate holder assembly and the anode.

Abstract: A copper filled semiconductor feature and method of forming the same having improved bulk properties the method including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

Abstract: An improvement in a copper damascene process is disclosed. The improvement comprises the step of projecting an electron beam on to a chemical mechanically polished material surface having copper filled etched trenches at a known angle of incidence with respect to the material surface for a known period of time, the electron beam having a beamwidth substantially covering the material surface and a known intensity.

Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.