Patents by Inventor Hung-Yi Kuo

Hung-Yi Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WAFER LEVEL PHOTONIC DEVICE DIES STRUCTURE AND METHOD OF MAKING THE SAME
    Publication number: 20160118562
    Abstract: A vertical Light Emitting Diode (LED) device includes an epi structure with a first-type-doped portion, a second-type-doped portion, and a quantum well structure between the first-type-doped and second-type-doped portions and a carrier structure with a plurality of conductive contact pads in electrical contact with the epi structure and a plurality of bonding pads on a side of the carrier structure distal the epi structure, in which the conductive contact pads are in electrical communication with the bonding pads using at least one of vias and a Redistribution Layer (RDL). The vertical LED device further includes a first insulating film on a side of the carrier structure proximal the epi structure and a second insulating film on a side of the carrier structure distal the epi structure.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Chih-Kuang YU, Hung-Yi KUO
  • 3D package with through substrate vias
    Patent number: 9305877
    Abstract: A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Chao-Wen Shih, Tsung-Yuan Yu, Min-Chien Hsiao
  • Method and apparatus for accurate die-to-wafer bonding
    Patent number: 9287478
    Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 15, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Semiconductor devices having guard ring structure and methods of manufacture thereof
    Patent number: 9245842
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Nien-Fang Wu, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Video wall
    Patent number: 9240163
    Abstract: A video wall, having screens, cables, synchronization detection modules and a central control unit. The cables are operative to carry image data to be displayed on the screens. The synchronization detection modules are coupled between the screens and the cables for detection of a feature symbol. The central control unit collects detection results from the synchronization detection modules, and the detection results are utilized in the adjustment of the image data before cable transmission. In this manner, image display synchronization between the screens is achieved. The synchronization detection modules may be implemented as connectors, each having a first end connected to a screen and a second end connected to a cable.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 19, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Hung-Yi Kuo, Chia-Hung Su
  • Capacitor in Post-Passivation Structures and Methods of Forming the Same
    Publication number: 20150380351
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Application
    Filed: September 11, 2015
    Publication date: December 31, 2015
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Wafer level photonic device die structure and method of making the same
    Patent number: 9224932
    Abstract: A structure includes a carrier substrate with a first side and a second side opposite the first side. The carrier substrate has a first contact pad and a second contact pad disposed over the first side and a third contact pad and a fourth contact pad disposed over the second side. The carrier substrate further includes a substrate and an insulation film disposed between the substrate and the first, second, third, and fourth contact pads. The structure further includes a first epi-structure and a second epi-structure disposed over the carrier substrate. The structure further includes a first metal element and a second metal element. Moreover, the structure further includes a first through-via and a second through-via. The first through-via and the second through-via extend through the first and second epi-structures respectively.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 29, 2015
    Assignee: TSMC SOLID STATE LIGHTING LTD.
    Inventors: Chih-Kuang Yu, Hung-Yi Kuo
  • Methods of forming through silicon via openings
    Patent number: 9224636
    Abstract: A method includes forming an opening in a substrate, and the opening completely extends through the substrate. A recast material is formed on sidewalls of the substrate exposed by the opening. A first chemical is applied in the opening to remove the recast material, wherein a residue of the first chemical remains on portions of the sidewalls after the applying of the first chemical. Moreover, A second chemical is applied in the opening to remove the residue of the first chemical, and the second chemical is different from the first chemical.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: December 29, 2015
    Assignee: TSMC SOLID STATE LIGHTING LTD.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chun-Lin Chang, Hsing-Kuo Hsia, Hung-Yi Kuo
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150364376
    Abstract: A semiconductor device includes a substrate and a bump. The substrate includes a first surface and a second surface. A notch is at the second surface and at a sidewall of the substrate. A depth of the notch is smaller than about half the thickness of the substrate. The bump is disposed on the first surface of the substrate.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: TSUNG-YUAN YU, HAO-YI TSAI, CHAO-WEN SHIH, HUNG-YI KUO, CHIA-CHUN MIAO
  • LED structure
    Patent number: 9184334
    Abstract: A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: November 10, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Shouli Steve Hsia, Chih-Kuang Yu, Ken Wen-Chien Fu, Hung-Yi Kuo, Hung-Chao Kao, Ming-Feng Wu, Fu-Chih Yang
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9136318
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Single Mask Package Apparatus
    Publication number: 20150255435
    Abstract: Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 ?m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo
  • Light emitting diode emitter substrate with highly reflective metal bonding
    Patent number: 9099632
    Abstract: A package structure includes: a substrate having a first side and a second side opposite to the first side; a metal layer disposed over at least a portion of the second side of the substrate; a light-reflective layer disposed over the first side of the substrate; and a photonic device bonded to the light-reflective layer from the first side. A segment of the metal layer extends through the substrate from the first side to the second side, and a portion of the substrate is completely enclosed in a cross-sectional view by the metal layer. The package structure is free of a bonding wire over the second side of the substrate.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 4, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Wen-Chien Fu, Hsing-Kuo Hsia, Chih-Kuang Yu, Ching-Hua Chiu, Hung-Yi Kuo
  • Inductor for Post Passivation Interconnect and A Method of Forming
    Publication number: 20150214148
    Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • De-noise circuit and de-noise method for differential signals and chip for receiving differential signals
    Patent number: 9041490
    Abstract: A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 26, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Chia-Hung Su, Tsung-Hsin Lin, Hung-Yi Kuo
  • Single mask package apparatus and method
    Patent number: 9041215
    Abstract: Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 ?m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150137355
    Abstract: A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.
    Type: Application
    Filed: March 31, 2014
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: TSUNG-YUAN YU, HAO-YI TSAI, CHAO-WEN SHIH, HUNG-YI KUO, PI-LAN CHANG
  • PACKAGED SEMICONDUCTOR DEVICE
    Publication number: 20150123267
    Abstract: A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: MIRNG-JI LII, HAO-YI TSAI, HSIEN-WEI CHEN, HUNG-YI KUO
  • Inductor for post passivation interconnect
    Patent number: 9000876
    Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • LED device with improved thermal performance
    Patent number: 8993447
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 31, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern