Abstract: A timing adjustment circuit and method thereof are disclosed. The timing adjustment circuit at least consists of a second timing adjustment unit, a multistage sample circuit, and a decision circuit for adjusting received timing of an output signal transmitted by a first chip and received by a second chip. The method takes advantage of the multistage sample circuit to receive a clock signal of receiving end so as to generate a plurality of sample clock signal. Later, according to the sample clock signals, sample output signals to generate a plurality of sampled signal. At last, make comparison of the sampled signals by the decision circuit in accordance with the output signals to generate a second adjustment signal being transmitted to the second timing adjustment unit for adjusting phase of a base clock to generate an adjusted receiving-end clock signal. Thus the receiving timing of the second chip to receive the output signal is adjusted.

Abstract: A signal adjustment circuit with a reference circuit is proposed in the present invention. The signal adjustment circuit is used to adjust a setting value of a first chip or a second chip. The first chip provides an output signal corresponding to an output value according to the setting value thereof. The second chip receives the output signal of the first chip according to the setting value thereof. The reference circuit has multiple reference voltages and compares the output signal of the first chip with the reference voltages to produce multiple comparison values. The comparison values are then passed to the decision unit. After that, the decision unit checks the comparison values according to the output value and produces an adjustment signal to adjust the setting value of the first chip or the second chip. In this way, the stability of transmission between the first and second chips is maintained.

Abstract: Chips with embedded capacitors for electromagnetic compatibility and related method are disclosed. In a chip, sudden electronic changes occur between power circuits for transmitting power of direct current biasing, and lead to electromagnetic interference of high frequency. In the present invention, capacitors for electromagnetic compatibility are directly embedded in the chip, that is, directly embedding build-in capacitors between power circuits of the chip. In this way, sudden electronic changes between power circuits can be effectively absorbed by the embedded capacitors, and electromagnetic interference is then reduced to provide better electromagnetic compatibility and protection.

Abstract: A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test value; utilizing the second chip to receive the test signal and utilizing the second chip to read the test signal to determine a value; and performing a comparison step for comparing the value with the test value to detect whether said value complies with the test value.

Abstract: A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.

Abstract: A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.

Abstract: A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.

Abstract: A control chip, a circuit and a method thereof with bus cycle inhibiting function is provided. A bus resource decode circuit is used to determine if a bus cycle picked up from a first bus is an internal bus cycle type of the control chip. If the bus cycle is found to be an internal bus cycle, an inhibit signal is transmitted to a bus bridging circuit after a logic computation inside a logic circuit so that a re-transmission of the internal bus cycle to a second bus is inhibited. In this manner, the second bus may step into an idle state and save some electrical power.

Abstract: A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.