Abstract: An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.

Abstract: A method of processing a substrate includes exposing the substrate to a boron-containing precursor to adsorb over the substrate, where the substrate includes a dielectric layer formed over a conductive layer, and the conductive layer is exposed at a bottom of a recess formed in the dielectric layer. The method includes exposing the adsorbed boron-containing precursor to a plasma and filling the recess with a conductive fill material bottom up by a vapor deposition process, where a vertical deposition rate of the conductive fill material is greater than a lateral deposition rate of the conductive fill material.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

Abstract: An electrical connector is configured to be assembled with a joint. The electrical connector includes an outer casing, a seat body and a plurality of insulation-displacement contacts. The outer casing includes a first casing and a second casing. The first casing includes an accommodation portion, a threaded portion and a connection portion, the accommodation portion and the threaded portion are integrally connected to each other via the connection portion. The accommodation portion is configured to be assembled with the joint, the threaded portion and the second casing are screwed with each other, and the first casing and the second casing together form an accommodation space. The seat body is disposed in the accommodation space. The insulation-displacement contacts are fixed to the seat body and extend to the accommodation portion.

Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Abstract: A switching power converter includes: a power stage circuit, including at least one transistor which is configured to operably switch an inductor to convert an input power to an output power; and an active EMI filter circuit, including at least one amplifier, wherein the at least one amplifier is configured to operably sense a noise input signal which is related to a switching noise caused by the switching of the power stage circuit, and amplify the noise input signal to generate a noise cancelling signal, wherein the noise cancelling signal is injected into an input node of the switching power converter, so as to suppress the switching noise and thus reducing EMI, wherein the input power is provided through the input node to the power stage circuit.

Abstract: A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Abstract: A method for recognizing a motion state of an object by using a millimeter wave radar having at least one antenna is disclosed. The method includes the following steps. A region is set to select an object in the region, wherein the object has M ranges and M azimuths between the object and the at least one antenna during a first motion time. Each of the M ranges and the M azimuths are projected on a two-dimensional (2D) plane to form M frames. The M frames are sequentially arranged into a first consecutive candidate frames having a time sequence. The first consecutive candidate frames are inputted into an artificial intelligence model to determine a motion state type of the first consecutive candidate frames.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor is configured to conduct in a first enable period. The second transistor is configured to conduct in a second enable period. The first transistor and the second transistor are coupled in series. The first enable period includes a first delay period, the second enable period and a second delay period that are arranged sequentially.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A method for manufacturing a nitrile butadiene rubber includes: subjecting a material composition containing water, butadiene, acrylonitrile, an emulsifying agent, an initiator, and a molecular weight regulator to an emulsion polymerization reaction, so as to form an emulsion; and adding a reactive antioxidant and a non-reactive antioxidant to the emulsion to form a mixture, followed by subjecting the mixture to a coagulation process, so as to form the nitrile butadiene rubber.

Abstract: The present disclosure provides various devices, systems, and methods for active shimming for an MRI system. For example, an MRI system can a first gradient coil, a second gradient coil, a third gradient coil, and a permanent magnet. The permanent magnet is configured to generate a magnetic field B0 having a low field strength. A method for active shimming the MRI system can include a set of candidate shimming configurations with first current values associated with the first gradient coil, second current values associated with the second gradient coil, and third current values associated with the third gradient coil. The method further includes applying, for each candidate shimming configuration, a pulse sequence; acquiring, for each pulse sequence, a magnetic resonance (MR) signal; determining, for each MR signal, a signal bandwidth based on a frequency domain of the MR signal; and designating a shimming configuration for the MRI system.

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Abstract: The present disclosure provides various devices, systems, and methods for iterative shimming in magnetic resonance imaging (MRI). In one aspect, a method of iterative shimming can include generating a field map of a magnetic field B0 from an MRI system. The MRI system can include a shim tray and an array of permanent magnets to generate the magnetic field B0. The shim tray can include slots to receive shim magnets. The method can further include shimming the MRI system by iteratively: applying the field map to a genetic algorithm to determine a set of slots to receive a set of shim magnets, installing the set of shim magnets in the set of slots, generating a next field map of the magnetic field B0, and either performing a next iteration based on the next field map or determining to not perform the next iteration based on the next field map.

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

Abstract: A power converter is coupled between a power source and multiple loads, and the power converter includes a first switch module. The switch module includes an inductor, a first switch, a second switch, a third switch, and a fourth switch. The first switch, the second switch, the third switch, and the fourth switch are configured to be turned on or turned off so that the inductor is stored energy or released energy to converter the power source into multiple voltages to the multiple loads.

Abstract: A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.

Abstract: A memory includes a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element and a second resistive memory element. Each of the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor includes a drain terminal, a source terminal and a gate terminal. The drain terminal of the third switch transistor is coupled to the source terminal of the first switch transistor. The drain terminal of the fourth switch transistor is coupled to the source terminal of the second switch transistor. The first resistive memory element is coupled to the source terminal of the fourth switch transistor and the source terminal of the first switch transistor. The second resistive memory element is coupled to the source terminal of the third switch transistor and the source terminal of the second switch transistor.

Abstract: A magnetic tunnel junction device includes a pillar structure including, from bottom to top, a bottom electrode and a magnetic tunnel junction structure, a top electrode overlying the magnetic tunnel junction structure, and a dielectric metal oxide layer extending from a sidewall of the pillar structure to a sidewall of the top electrode. The magnetic tunnel junction structure contains a reference magnetization layer including a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer including a second ferromagnetic material. The top electrode includes a metallic material containing a nonmagnetic metal element. The dielectric metal oxide layer may be formed by performing an oxidation process that oxidizes a residual metal film after a focused ion beam etch process, and eliminates conductive paths from surfaces of the pillar structure.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.